inorder: switch out buffer
add buffer for instructions to switch out to in a pipeline stage can't squash the instruction and remove the pipeline so we kind of need to 'suspend' an instruction at the stage while the memory stall resolves for the switch on cache miss model
This commit is contained in:
Korey Sewell
parent
a892af7b26
commit
e8312ab6f7
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@ -44,6 +44,9 @@ PipelineStage::PipelineStage(Params *params, unsigned stage_num)
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stageBufferMax(ThePipeline::interStageBuffSize[stage_num]),
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prevStageValid(false), nextStageValid(false)
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{
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switchedOutBuffer.resize(ThePipeline::MaxThreads);
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switchedOutValid.resize(ThePipeline::MaxThreads);
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init(params);
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}
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@ -267,7 +270,8 @@ PipelineStage::isBlocked(ThreadID tid)
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bool
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PipelineStage::block(ThreadID tid)
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{
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DPRINTF(InOrderStage, "[tid:%d]: Blocking, sending block signal back to previous stages.\n", tid);
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DPRINTF(InOrderStage, "[tid:%d]: Blocking, sending block signal back to "
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"previous stages.\n", tid);
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// Add the current inputs to the skid buffer so they can be
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// reprocessed when this stage unblocks.
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@ -296,7 +300,8 @@ PipelineStage::block(ThreadID tid)
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void
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PipelineStage::blockDueToBuffer(ThreadID tid)
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{
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DPRINTF(InOrderStage, "[tid:%d]: Blocking instructions from passing to next stage.\n", tid);
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DPRINTF(InOrderStage, "[tid:%d]: Blocking instructions from passing to "
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"next stage.\n", tid);
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if (stageStatus[tid] != Blocked) {
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// Set the status to Blocked.
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@ -334,8 +339,9 @@ PipelineStage::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
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{
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if (cpu->squashSeqNum[tid] < inst->seqNum &&
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cpu->lastSquashCycle[tid] == curTick){
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DPRINTF(Resource, "Ignoring [sn:%i] squash signal due to another stage's squash "
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"signal for after [sn:%i].\n", inst->seqNum, cpu->squashSeqNum[tid]);
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DPRINTF(Resource, "Ignoring [sn:%i] squash signal due to another "
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"stage's squash signal for after [sn:%i].\n", inst->seqNum,
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cpu->squashSeqNum[tid]);
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} else {
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// Send back mispredict information.
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toPrevStages->stageInfo[stageNum][tid].branchMispredict = true;
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@ -346,20 +352,28 @@ PipelineStage::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
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#if ISA_HAS_DELAY_SLOT
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toPrevStages->stageInfo[stageNum][tid].branchTaken = inst->readNextNPC() !=
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toPrevStages->stageInfo[stageNum][tid].branchTaken =
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inst->readNextNPC() !=
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(inst->readNextPC() + sizeof(TheISA::MachInst));
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toPrevStages->stageInfo[stageNum][tid].bdelayDoneSeqNum = inst->bdelaySeqNum;
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toPrevStages->stageInfo[stageNum][tid].bdelayDoneSeqNum =
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inst->bdelaySeqNum;
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InstSeqNum squash_seq_num = inst->bdelaySeqNum;
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#else
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toPrevStages->stageInfo[stageNum][tid].branchTaken = inst->readNextPC() !=
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toPrevStages->stageInfo[stageNum][tid].branchTaken =
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inst->readNextPC() !=
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(inst->readPC() + sizeof(TheISA::MachInst));
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toPrevStages->stageInfo[stageNum][tid].bdelayDoneSeqNum = inst->seqNum;
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InstSeqNum squash_seq_num = inst->seqNum;
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#endif
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DPRINTF(InOrderStage, "Target being re-set to %08p\n", inst->readPredTarg());
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DPRINTF(InOrderStage, "[tid:%i]: Squashing after [sn:%i], due to [sn:%i] "
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"branch.\n", tid, squash_seq_num, inst->seqNum);
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DPRINTF(InOrderStage, "Target being re-set to %08p\n",
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inst->readPredTarg());
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DPRINTF(InOrderStage, "[tid:%i]: Squashing after [sn:%i], "
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"due to [sn:%i] branch.\n", tid, squash_seq_num,
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inst->seqNum);
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// Save squash num for later stage use
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cpu->squashSeqNum[tid] = squash_seq_num;
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@ -394,8 +408,8 @@ PipelineStage::squash(InstSeqNum squash_seq_num, ThreadID tid)
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squashPrevStageInsts(squash_seq_num, tid);
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DPRINTF(InOrderStage, "[tid:%i]: Removing instructions from incoming stage skidbuffer.\n",
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tid);
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DPRINTF(InOrderStage, "[tid:%i]: Removing instructions from incoming stage"
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" skidbuffer.\n", tid);
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while (!skidBuffer[tid].empty()) {
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if (skidBuffer[tid].front()->seqNum <= squash_seq_num) {
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DPRINTF(InOrderStage, "[tid:%i]: Cannot remove skidBuffer "
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@ -404,8 +418,9 @@ PipelineStage::squash(InstSeqNum squash_seq_num, ThreadID tid)
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skidBuffer[tid].size());
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break;
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}
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DPRINTF(InOrderStage, "[tid:%i]: Removing instruction, [sn:%i] PC %08p.\n",
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tid, skidBuffer[tid].front()->seqNum, skidBuffer[tid].front()->PC);
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DPRINTF(InOrderStage, "[tid:%i]: Removing instruction, [sn:%i] "
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" PC %08p.\n", tid, skidBuffer[tid].front()->seqNum,
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skidBuffer[tid].front()->PC);
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skidBuffer[tid].pop();
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}
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@ -427,7 +442,8 @@ PipelineStage::stageBufferAvail()
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int avail = stageBufferMax - total -0;// incoming_insts;
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if (avail < 0)
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fatal("stageNum %i:stageBufferAvail() < 0...stBMax=%i,total=%i,incoming=%i=>%i",
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fatal("stageNum %i:stageBufferAvail() < 0..."
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"stBMax=%i,total=%i,incoming=%i=>%i",
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stageNum, stageBufferMax, total, incoming_insts, avail);
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return avail;
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@ -443,7 +459,8 @@ PipelineStage::canSendInstToStage(unsigned stage_num)
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}
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if (!buffer_avail && nextStageQueueValid(stage_num)) {
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DPRINTF(InOrderStall, "STALL: No room in stage %i buffer.\n", stageNum + 1);
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DPRINTF(InOrderStall, "STALL: No room in stage %i buffer.\n",
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stageNum + 1);
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}
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return buffer_avail;
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@ -461,8 +478,9 @@ PipelineStage::skidInsert(ThreadID tid)
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assert(tid == inst->threadNumber);
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DPRINTF(InOrderStage,"[tid:%i]: Inserting [sn:%lli] PC:%#x into stage skidBuffer %i\n",
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tid, inst->seqNum, inst->readPC(), inst->threadNumber);
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DPRINTF(InOrderStage,"[tid:%i]: Inserting [sn:%lli] PC:%#x into stage "
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"skidBuffer %i\n", tid, inst->seqNum, inst->readPC(),
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inst->threadNumber);
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skidBuffer[tid].push(inst);
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}
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@ -547,16 +565,16 @@ PipelineStage::sortInsts()
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for (int i = 0; i < insts_from_prev_stage; ++i) {
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if (prevStage->insts[i]->isSquashed()) {
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DPRINTF(InOrderStage, "[tid:%i]: Ignoring squashed [sn:%i], not inserting "
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"into stage buffer.\n",
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DPRINTF(InOrderStage, "[tid:%i]: Ignoring squashed [sn:%i], "
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"not inserting into stage buffer.\n",
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prevStage->insts[i]->readTid(),
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prevStage->insts[i]->seqNum);
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continue;
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}
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DPRINTF(InOrderStage, "[tid:%i]: Inserting [sn:%i] into stage buffer.\n",
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prevStage->insts[i]->readTid(),
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DPRINTF(InOrderStage, "[tid:%i]: Inserting [sn:%i] into stage "
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"buffer.\n", prevStage->insts[i]->readTid(),
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prevStage->insts[i]->seqNum);
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ThreadID tid = prevStage->insts[i]->threadNumber;
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@ -611,8 +629,8 @@ PipelineStage::checkSignalsAndUpdate(ThreadID tid)
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// Check for squash from later pipeline stages
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for (int stage_idx=stageNum; stage_idx < NumStages; stage_idx++) {
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if (fromNextStages->stageInfo[stage_idx][tid].squash) {
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DPRINTF(InOrderStage, "[tid:%u]: Squashing instructions due to squash "
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"from stage %u.\n", tid, stage_idx);
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DPRINTF(InOrderStage, "[tid:%u]: Squashing instructions due to "
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"squash from stage %u.\n", tid, stage_idx);
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InstSeqNum squash_seq_num = fromNextStages->
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stageInfo[stage_idx][tid].bdelayDoneSeqNum;
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squash(squash_seq_num, tid);
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@ -625,8 +643,8 @@ PipelineStage::checkSignalsAndUpdate(ThreadID tid)
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}
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if (stageStatus[tid] == Blocked) {
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DPRINTF(InOrderStage, "[tid:%u]: Done blocking, switching to unblocking.\n",
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tid);
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DPRINTF(InOrderStage, "[tid:%u]: Done blocking, switching to "
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"unblocking.\n", tid);
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stageStatus[tid] = Unblocking;
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@ -637,15 +655,15 @@ PipelineStage::checkSignalsAndUpdate(ThreadID tid)
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if (stageStatus[tid] == Squashing) {
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if (!skidBuffer[tid].empty()) {
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DPRINTF(InOrderStage, "[tid:%u]: Done squashing, switching to unblocking.\n",
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tid);
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DPRINTF(InOrderStage, "[tid:%u]: Done squashing, switching to "
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"unblocking.\n", tid);
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stageStatus[tid] = Unblocking;
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} else {
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// Switch status to running if stage isn't being told to block or
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// squash this cycle.
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DPRINTF(InOrderStage, "[tid:%u]: Done squashing, switching to running.\n",
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tid);
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DPRINTF(InOrderStage, "[tid:%u]: Done squashing, switching to "
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"running.\n", tid);
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stageStatus[tid] = Running;
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}
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@ -717,13 +735,13 @@ PipelineStage::unsetResStall(ResReqPtr res_req, ThreadID tid)
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}
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if (stalls[tid].resources.size() == 0) {
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DPRINTF(InOrderStage, "[tid:%u]: There are no remaining resource stalls.\n",
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tid);
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DPRINTF(InOrderStage, "[tid:%u]: There are no remaining resource"
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"stalls.\n", tid);
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}
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}
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// @TODO: Update How we handled threads in CPU. Maybe threads shouldnt be handled
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// one at a time, but instead first come first serve by instruction?
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// @TODO: Update How we handled threads in CPU. Maybe threads shouldnt be
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// handled one at a time, but instead first come first serve by instruction?
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// Questions are how should a pipeline stage handle thread-specific stalls &
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// pipeline squashes
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void
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@ -749,8 +767,8 @@ PipelineStage::processStage(bool &status_change)
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DPRINTF(InOrderStage, "%i left in stage %i incoming buffer.\n", skidSize(),
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stageNum);
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DPRINTF(InOrderStage, "%i available in stage %i incoming buffer.\n", stageBufferAvail(),
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stageNum);
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DPRINTF(InOrderStage, "%i available in stage %i incoming buffer.\n",
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stageBufferAvail(), stageNum);
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}
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void
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@ -828,8 +846,8 @@ PipelineStage::processInsts(ThreadID tid)
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inst = insts_to_stage.front();
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DPRINTF(InOrderStage, "[tid:%u]: Processing instruction [sn:%lli] with "
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"PC %#x\n",
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DPRINTF(InOrderStage, "[tid:%u]: Processing instruction [sn:%lli] "
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"with PC %#x\n",
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tid, inst->seqNum, inst->readPC());
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if (inst->isSquashed()) {
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@ -856,8 +874,8 @@ PipelineStage::processInsts(ThreadID tid)
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// Send to Next Stage or Break Loop
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if (nextStageValid && !sendInstToNextStage(inst)) {
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DPRINTF(InOrderStage, "[tid:%i] [sn:%i] unable to proceed to stage %i.\n",
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tid, inst->seqNum,inst->nextStage);
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DPRINTF(InOrderStage, "[tid:%i] [sn:%i] unable to proceed to stage"
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" %i.\n", tid, inst->seqNum,inst->nextStage);
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break;
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}
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@ -897,14 +915,15 @@ PipelineStage::processInstSchedule(DynInstPtr inst)
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int res_num = inst->nextResource();
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DPRINTF(InOrderStage, "[tid:%i]: [sn:%i]: sending request to %s.\n",
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tid, inst->seqNum, cpu->resPool->name(res_num));
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DPRINTF(InOrderStage, "[tid:%i]: [sn:%i]: sending request to %s."
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"\n", tid, inst->seqNum, cpu->resPool->name(res_num));
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ResReqPtr req = cpu->resPool->request(res_num, inst);
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if (req->isCompleted()) {
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DPRINTF(InOrderStage, "[tid:%i]: [sn:%i] request to %s completed.\n",
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tid, inst->seqNum, cpu->resPool->name(res_num));
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DPRINTF(InOrderStage, "[tid:%i]: [sn:%i] request to %s "
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"completed.\n", tid, inst->seqNum,
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cpu->resPool->name(res_num));
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if (req->fault == NoFault) {
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inst->popSchedEntry();
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@ -913,8 +932,8 @@ PipelineStage::processInstSchedule(DynInstPtr inst)
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curTick, req->fault->name());
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}
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} else {
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DPRINTF(InOrderStage, "[tid:%i]: [sn:%i] request to %s failed.\n",
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tid, inst->seqNum, cpu->resPool->name(res_num));
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DPRINTF(InOrderStage, "[tid:%i]: [sn:%i] request to %s failed."
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"\n", tid, inst->seqNum, cpu->resPool->name(res_num));
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last_req_completed = false;
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@ -956,12 +975,12 @@ PipelineStage::sendInstToNextStage(DynInstPtr inst)
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assert(next_stage >= 1);
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assert(prev_stage >= 0);
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DPRINTF(InOrderStage, "[tid:%u]: Attempting to send instructions to stage %u.\n", tid,
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stageNum+1);
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DPRINTF(InOrderStage, "[tid:%u]: Attempting to send instructions to "
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"stage %u.\n", tid, stageNum+1);
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if (!canSendInstToStage(inst->nextStage)) {
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DPRINTF(InOrderStage, "[tid:%u]: Could not send instruction to stage %u.\n", tid,
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stageNum+1);
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DPRINTF(InOrderStage, "[tid:%u]: Could not send instruction to "
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"stage %u.\n", tid, stageNum+1);
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return false;
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}
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@ -969,12 +988,14 @@ PipelineStage::sendInstToNextStage(DynInstPtr inst)
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if (nextStageQueueValid(inst->nextStage - 1)) {
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if (inst->seqNum > cpu->squashSeqNum[tid] &&
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curTick == cpu->lastSquashCycle[tid]) {
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DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, skipping insertion "
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"into stage %i queue.\n", tid, inst->seqNum, inst->nextStage);
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DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, skipping "
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"insertion into stage %i queue.\n", tid, inst->seqNum,
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inst->nextStage);
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} else {
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if (nextStageValid) {
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DPRINTF(InOrderStage, "[tid:%u] %i slots available in next stage buffer.\n",
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tid, cpu->pipelineStage[next_stage]->stageBufferAvail());
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DPRINTF(InOrderStage, "[tid:%u] %i slots available in next "
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"stage buffer.\n", tid,
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cpu->pipelineStage[next_stage]->stageBufferAvail());
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}
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DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: being placed into "
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@ -982,11 +1003,13 @@ PipelineStage::sendInstToNextStage(DynInstPtr inst)
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tid, inst->seqNum, toNextStageIndex,
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cpu->pipelineStage[prev_stage]->nextStageQueue->id());
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int next_stage_idx = cpu->pipelineStage[prev_stage]->nextStage->size;
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int next_stage_idx =
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cpu->pipelineStage[prev_stage]->nextStage->size;
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// Place instructions in inter-stage communication struct for the next
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// Place instructions in inter-stage communication struct for next
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// pipeline stage to read next cycle
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cpu->pipelineStage[prev_stage]->nextStage->insts[next_stage_idx] = inst;
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cpu->pipelineStage[prev_stage]->nextStage->insts[next_stage_idx]
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= inst;
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++(cpu->pipelineStage[prev_stage]->nextStage->size);
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@ -240,6 +240,8 @@ class PipelineStage
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*/
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virtual void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
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virtual void squashDueToMemStall(DynInstPtr &inst, ThreadID tid);
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/** Squash instructions from stage buffer */
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virtual void squashPrevStageInsts(InstSeqNum squash_seq_num, ThreadID tid);
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@ -259,19 +261,28 @@ class PipelineStage
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/** List of active thread ids */
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std::list<ThreadID> *activeThreads;
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/** Buffer of instructions switched out to mem-stall.
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* Only used when using SwitchOnCacheMiss threading model
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* Used as 1-to-1 mapping between ThreadID and Entry.
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*/
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std::vector<DynInstPtr> switchedOutBuffer;
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std::vector<bool> switchedOutValid;
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/** Queue of all instructions coming from previous stage on this cycle. */
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std::queue<DynInstPtr> insts[ThePipeline::MaxThreads];
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/** Queue of instructions that are finished processing and ready to go next stage.
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* This is used to prevent from processing an instrution more than once on any
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* stage. NOTE: It is up to the PROGRAMMER must manage this as a queue
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/** Queue of instructions that are finished processing and ready to go
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* next stage. This is used to prevent from processing an instrution more
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* than once on any stage. NOTE: It is up to the PROGRAMMER must manage
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* this as a queue
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*/
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std::list<DynInstPtr> instsToNextStage;
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/** Skid buffer between previous stage and this one. */
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std::queue<DynInstPtr> skidBuffer[ThePipeline::MaxThreads];
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/** Instruction used to signify that there is no *real* instruction in buffer slot */
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/** Instruction used to signify that there is no *real* instruction in
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* buffer slot */
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DynInstPtr dummyBufferInst;
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/** SeqNum of Squashing Branch Delay Instruction (used for MIPS) */
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