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Fix #include lines for renamed cache files.

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--HG--
extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5
This commit is contained in:
Steve Reinhardt 2008-02-10 14:45:25 -08:00
parent d56e77c180
commit 9d7a69c582
33 changed files with 49 additions and 52 deletions
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3
src/cpu/memtest/memtest.cc
View file

@ -39,12 +39,9 @@
#include "base/misc.hh"
#include "base/statistics.hh"
#include "cpu/memtest/memtest.hh"
//#include "cpu/simple_thread.hh"
//#include "mem/cache/base_cache.hh"
#include "mem/mem_object.hh"
#include "mem/port.hh"
#include "mem/packet.hh"
//#include "mem/physical.hh"
#include "mem/request.hh"
#include "sim/sim_events.hh"
#include "sim/stats.hh"

2
src/cpu/ozone/simple_cpu_builder.cc
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@ -35,7 +35,7 @@
#include "cpu/ozone/cpu_impl.hh"
#include "cpu/ozone/simple_impl.hh"
#include "cpu/ozone/simple_params.hh"
#include "mem/cache/base_cache.hh"
#include "mem/cache/base.hh"
#include "sim/SimpleOzoneCPU.hh"
#include "sim/process.hh"
#include "sim/sim_object.hh"

4
src/mem/cache/base.cc vendored
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@ -35,8 +35,8 @@
#include "cpu/base.hh"
#include "cpu/smt.hh"
#include "mem/cache/base_cache.hh"
#include "mem/cache/miss/mshr.hh"
#include "mem/cache/base.hh"
#include "mem/cache/mshr.hh"
using namespace std;

2
src/mem/cache/base.hh vendored
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@ -47,7 +47,7 @@
#include "base/misc.hh"
#include "base/statistics.hh"
#include "base/trace.hh"
#include "mem/cache/miss/mshr_queue.hh"
#include "mem/cache/mshr_queue.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/tport.hh"

2
src/mem/cache/blk.cc vendored
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@ -27,7 +27,7 @@
*/
#include "base/cprintf.hh"
#include "mem/cache/cache_blk.hh"
#include "mem/cache/blk.hh"
void
CacheBlkPrintWrapper::print(std::ostream &os, int verbosity,

8
src/mem/cache/builder.cc vendored
View file

@ -39,7 +39,7 @@
#include "enums/Prefetch.hh"
#include "mem/config/cache.hh"
#include "mem/config/prefetch.hh"
#include "mem/cache/base_cache.hh"
#include "mem/cache/base.hh"
#include "mem/cache/cache.hh"
#include "mem/bus.hh"
#include "params/BaseCache.hh"
@ -67,13 +67,13 @@
//Prefetcher Headers
#if defined(USE_GHB)
#include "mem/cache/prefetch/ghb_prefetcher.hh"
#include "mem/cache/prefetch/ghb.hh"
#endif
#if defined(USE_TAGGED)
#include "mem/cache/prefetch/tagged_prefetcher.hh"
#include "mem/cache/prefetch/tagged.hh"
#endif
#if defined(USE_STRIDED)
#include "mem/cache/prefetch/stride_prefetcher.hh"
#include "mem/cache/prefetch/stride.hh"
#endif

6
src/mem/cache/cache.hh vendored
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@ -41,9 +41,9 @@
#include "base/misc.hh" // fatal, panic, and warn
#include "mem/cache/base_cache.hh"
#include "mem/cache/cache_blk.hh"
#include "mem/cache/miss/mshr.hh"
#include "mem/cache/base.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/mshr.hh"
#include "sim/eventq.hh"

6
src/mem/cache/cache_impl.hh vendored
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@ -42,9 +42,9 @@
#include "base/range_ops.hh"
#include "mem/cache/cache.hh"
#include "mem/cache/cache_blk.hh"
#include "mem/cache/miss/mshr.hh"
#include "mem/cache/prefetch/base_prefetcher.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/mshr.hh"
#include "mem/cache/prefetch/base.hh"
#include "sim/sim_exit.hh" // for SimExitEvent

2
src/mem/cache/mshr.cc vendored
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@ -39,7 +39,7 @@
#include <vector>
#include <algorithm>
#include "mem/cache/miss/mshr.hh"
#include "mem/cache/mshr.hh"
#include "sim/core.hh" // for curTick
#include "sim/host.hh"
#include "base/misc.hh"

2
src/mem/cache/mshr_queue.cc vendored
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@ -32,7 +32,7 @@
* Definition of MSHRQueue class functions.
*/
#include "mem/cache/miss/mshr_queue.hh"
#include "mem/cache/mshr_queue.hh"
using namespace std;

2
src/mem/cache/mshr_queue.hh vendored
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@ -38,7 +38,7 @@
#include <vector>
#include "mem/packet.hh"
#include "mem/cache/miss/mshr.hh"
#include "mem/cache/mshr.hh"
/**
* A Class for maintaining a list of pending and allocated memory requests.

4
src/mem/cache/prefetch/base.cc vendored
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@ -34,8 +34,8 @@
*/
#include "base/trace.hh"
#include "mem/cache/base_cache.hh"
#include "mem/cache/prefetch/base_prefetcher.hh"
#include "mem/cache/base.hh"
#include "mem/cache/prefetch/base.hh"
#include "mem/request.hh"
#include <list>

2
src/mem/cache/prefetch/ghb.cc vendored
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@ -34,7 +34,7 @@
* GHB Prefetcher implementation.
*/
#include "mem/cache/prefetch/ghb_prefetcher.hh"
#include "mem/cache/prefetch/ghb.hh"
#include "arch/isa_traits.hh"
void

2
src/mem/cache/prefetch/ghb.hh vendored
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@ -36,7 +36,7 @@
#ifndef __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__
#define __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__
#include "mem/cache/prefetch/base_prefetcher.hh"
#include "mem/cache/prefetch/base.hh"
class GHBPrefetcher : public BasePrefetcher
{

2
src/mem/cache/prefetch/stride.cc vendored
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@ -34,7 +34,7 @@
* Stride Prefetcher template instantiations.
*/
#include "mem/cache/prefetch/stride_prefetcher.hh"
#include "mem/cache/prefetch/stride.hh"
void
StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,

2
src/mem/cache/prefetch/stride.hh vendored
View file

@ -36,7 +36,7 @@
#ifndef __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
#define __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
#include "mem/cache/prefetch/base_prefetcher.hh"
#include "mem/cache/prefetch/base.hh"
class StridePrefetcher : public BasePrefetcher
{

2
src/mem/cache/prefetch/tagged.cc vendored
View file

@ -34,7 +34,7 @@
*/
#include "arch/isa_traits.hh"
#include "mem/cache/prefetch/tagged_prefetcher.hh"
#include "mem/cache/prefetch/tagged.hh"
TaggedPrefetcher::TaggedPrefetcher(const BaseCacheParams *p)
: BasePrefetcher(p),

2
src/mem/cache/prefetch/tagged.hh vendored
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@ -36,7 +36,7 @@
#ifndef __MEM_CACHE_PREFETCH_TAGGED_PREFETCHER_HH__
#define __MEM_CACHE_PREFETCH_TAGGED_PREFETCHER_HH__
#include "mem/cache/prefetch/base_prefetcher.hh"
#include "mem/cache/prefetch/base.hh"
class TaggedPrefetcher : public BasePrefetcher
{

4
src/mem/cache/tags/base.cc vendored
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@ -34,9 +34,9 @@
* Definitions of BaseTags.
*/
#include "mem/cache/tags/base_tags.hh"
#include "mem/cache/tags/base.hh"
#include "mem/cache/base_cache.hh"
#include "mem/cache/base.hh"
#include "cpu/smt.hh" //maxThreadsPerCPU
#include "sim/sim_exit.hh"

4
src/mem/cache/tags/fa_lru.hh vendored
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@ -38,10 +38,10 @@
#include <list>
#include "mem/cache/cache_blk.hh"
#include "mem/cache/blk.hh"
#include "mem/packet.hh"
#include "base/hashmap.hh"
#include "mem/cache/tags/base_tags.hh"
#include "mem/cache/tags/base.hh"
/**
* A fully associative cache block.

2
src/mem/cache/tags/iic.cc vendored
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@ -39,7 +39,7 @@
#include <math.h>
#include "mem/cache/base_cache.hh"
#include "mem/cache/base.hh"
#include "mem/cache/tags/iic.hh"
#include "base/intmath.hh"
#include "sim/core.hh" // for curTick

6
src/mem/cache/tags/iic.hh vendored
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@ -39,11 +39,11 @@
#include <list>
#include <vector>
#include "mem/cache/cache_blk.hh"
#include "mem/cache/tags/repl/repl.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/tags/iic_repl/repl.hh"
#include "mem/packet.hh"
#include "base/statistics.hh"
#include "mem/cache/tags/base_tags.hh"
#include "mem/cache/tags/base.hh"
class BaseCache; // Forward declaration

2
src/mem/cache/tags/iic_repl/gen.cc vendored
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@ -38,7 +38,7 @@
#include "base/misc.hh"
#include "mem/cache/tags/iic.hh"
#include "mem/cache/tags/repl/gen.hh"
#include "mem/cache/tags/iic_repl/gen.hh"
#include "params/GenRepl.hh"
#include "sim/host.hh"

2
src/mem/cache/tags/iic_repl/gen.hh vendored
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@ -39,7 +39,7 @@
#include <list>
#include "base/statistics.hh"
#include "mem/cache/tags/repl/repl.hh"
#include "mem/cache/tags/iic_repl/repl.hh"
#include "params/GenRepl.hh"
/**

2
src/mem/cache/tags/lru.cc vendored
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@ -35,7 +35,7 @@
#include <string>
#include "mem/cache/base_cache.hh"
#include "mem/cache/base.hh"
#include "base/intmath.hh"
#include "mem/cache/tags/lru.hh"
#include "sim/core.hh"

4
src/mem/cache/tags/lru.hh vendored
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@ -39,10 +39,10 @@
#include <cstring>
#include <list>
#include "mem/cache/cache_blk.hh" // base class
#include "mem/cache/blk.hh" // base class
#include "mem/packet.hh" // for inlined functions
#include <assert.h>
#include "mem/cache/tags/base_tags.hh"
#include "mem/cache/tags/base.hh"
class BaseCache;

2
src/mem/cache/tags/split.cc vendored
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@ -41,7 +41,7 @@
#include "base/intmath.hh"
#include "base/output.hh"
#include "base/trace.hh"
#include "mem/cache/base_cache.hh"
#include "mem/cache/base.hh"
#include "mem/cache/tags/split.hh"
#include "mem/cache/tags/split_lifo.hh"
#include "mem/cache/tags/split_lru.hh"

4
src/mem/cache/tags/split.hh vendored
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@ -39,11 +39,11 @@
#include <cstring>
#include <list>
#include "mem/cache/cache_blk.hh" // base class
#include "mem/cache/blk.hh" // base class
#include "mem/cache/tags/split_blk.hh"
#include "mem/packet.hh" // for inlined functions
#include <assert.h>
#include "mem/cache/tags/base_tags.hh"
#include "mem/cache/tags/base.hh"
#include "base/hashmap.hh"
class BaseCache;

2
src/mem/cache/tags/split_blk.hh vendored
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@ -36,7 +36,7 @@
#ifndef __SPLIT_BLK_HH__
#define __SPLIT_BLK_HH__
#include "mem/cache/cache_blk.hh" // base class
#include "mem/cache/blk.hh" // base class
/**
* Split cache block.

2
src/mem/cache/tags/split_lifo.cc vendored
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@ -35,7 +35,7 @@
#include <string>
#include "mem/cache/base_cache.hh"
#include "mem/cache/base.hh"
#include "base/intmath.hh"
#include "mem/cache/tags/split_lifo.hh"
#include "sim/core.hh"

4
src/mem/cache/tags/split_lifo.hh vendored
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@ -39,12 +39,12 @@
#include <cstring>
#include <list>
#include "mem/cache/cache_blk.hh" // base class
#include "mem/cache/blk.hh" // base class
#include "mem/cache/tags/split_blk.hh"
#include "mem/packet.hh" // for inlined functions
#include "base/hashmap.hh"
#include <assert.h>
#include "mem/cache/tags/base_tags.hh"
#include "mem/cache/tags/base.hh"
class BaseCache;

2
src/mem/cache/tags/split_lru.cc vendored
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@ -35,7 +35,7 @@
#include <string>
#include "mem/cache/base_cache.hh"
#include "mem/cache/base.hh"
#include "base/intmath.hh"
#include "mem/cache/tags/split_lru.hh"
#include "sim/core.hh"

4
src/mem/cache/tags/split_lru.hh vendored
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@ -39,11 +39,11 @@
#include <cstring>
#include <list>
#include "mem/cache/cache_blk.hh" // base class
#include "mem/cache/blk.hh" // base class
#include "mem/cache/tags/split_blk.hh"
#include "mem/packet.hh" // for inlined functions
#include <assert.h>
#include "mem/cache/tags/base_tags.hh"
#include "mem/cache/tags/base.hh"
class BaseCache;