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inorder-mem: clean up allocation/deletion of requests/packets

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This commit is contained in:
Korey Sewell 2009-05-12 15:01:15 -04:00
parent 1c7e988272
commit c9a03f549b
5 changed files with 36 additions and 16 deletions
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14
src/cpu/inorder/inorder_dyn_inst.cc
View file

@ -108,7 +108,9 @@ InOrderDynInst::setMachInst(ExtMachInst machInst)
void
InOrderDynInst::initVars()
{
req = NULL;
fetchMemReq = NULL;
dataMemReq = NULL;
effAddr = 0;
physEffAddr = 0;
@ -170,8 +172,14 @@ InOrderDynInst::initVars()
InOrderDynInst::~InOrderDynInst()
{
if (req) {
delete req;
if (fetchMemReq != 0x0) {
delete fetchMemReq;
fetchMemReq = NULL;
}
if (dataMemReq != 0x0) {
delete dataMemReq;
dataMemReq = NULL;
}
if (traceData) {

3
src/cpu/inorder/inorder_dyn_inst.hh
View file

@ -634,7 +634,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted
/** Read Effective Address from instruction & do memory access */
Fault memAccess();
RequestPtr memReq;
RequestPtr fetchMemReq;
RequestPtr dataMemReq;
bool memAddrReady;

7
src/cpu/inorder/resources/cache_unit.cc
View file

@ -252,6 +252,8 @@ CacheUnit::execute(int slot_num)
break;
case CompleteFetch:
// @TODO: MOVE Functionality of handling fetched data into 'fetch unit'
// let cache-unit just be responsible for transferring data.
if (cache_req->isMemAccComplete()) {
DPRINTF(InOrderCachePort,
"[tid:%i]: Completing Fetch Access for [sn:%i]\n",
@ -284,6 +286,8 @@ CacheUnit::execute(int slot_num)
inst->traceData->setPC(inst->readPC());
}
delete cache_req->dataPkt;
cache_req->done();
} else {
DPRINTF(InOrderCachePort,
@ -481,6 +485,7 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
cache_pkt->cacheReq->getInst()->seqNum);
cache_pkt->cacheReq->done();
delete cache_pkt;
return;
}
@ -543,6 +548,8 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
getMemData(cache_pkt));
}
delete cache_pkt;
}
cache_req->setMemAccPending(false);

11
src/cpu/inorder/resources/cache_unit.hh
View file

@ -246,7 +246,13 @@ class CacheRequest : public ResourceRequest
: ResourceRequest(cres, inst, stage_num, res_idx, slot_num, cmd),
pktCmd(pkt_cmd), memAccComplete(false), memAccPending(false)
{
memReq = inst->memReq;
if (cmd == CacheUnit::InitiateFetch ||
cmd == CacheUnit::CompleteFetch ||
cmd == CacheUnit::Fetch) {
memReq = inst->fetchMemReq;
} else {
memReq = inst->dataMemReq;
}
reqData = new uint8_t[req_size];
retryPkt = NULL;
@ -273,9 +279,6 @@ class CacheRequest : public ResourceRequest
delete retryPkt;
}
#endif
if (memReq)
delete memReq;
}
virtual PacketDataPtr getData()

17
src/cpu/inorder/resources/tlb_unit.hh
View file

@ -106,21 +106,22 @@ class TLBUnitRequest : public ResourceRequest {
aligned_addr = inst->getMemAddr();
req_size = sizeof(TheISA::MachInst);
flags = 0;
inst->fetchMemReq = new Request(inst->readTid(), aligned_addr, req_size,
flags, inst->readPC(), res->cpu->readCpuId(), inst->readTid());
memReq = inst->fetchMemReq;
} else {
aligned_addr = inst->getMemAddr();;
req_size = inst->getMemAccSize();
flags = inst->getMemFlags();
}
if (req_size == 0 && (inst->isDataPrefetch() || inst->isInstPrefetch())) {
req_size = 8;
}
if (req_size == 0 && (inst->isDataPrefetch() || inst->isInstPrefetch())) {
req_size = 8;
}
// @TODO: Add Vaddr & Paddr functions
inst->memReq = new Request(inst->readTid(), aligned_addr, req_size,
inst->dataMemReq = new Request(inst->readTid(), aligned_addr, req_size,
flags, inst->readPC(), res->cpu->readCpuId(), inst->readTid());
memReq = inst->memReq;
memReq = inst->dataMemReq;
}
}
RequestPtr memReq;