X86: Hook in the M5 pseudo insts.
This commit is contained in:
Gabe Black
parent
115b1a7ed3
commit
b23633ad1b
5 changed files with 104 additions and 3 deletions
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@ -163,8 +163,96 @@
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}
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0x02: lar_Gv_Ew();
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0x03: lsl_Gv_Ew();
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//sandpile.org doesn't seem to know what this is... ?
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0x04: loadall_or_reset_or_hang();
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// sandpile.org doesn't seem to know what this is...? We'll
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// use it for pseudo instructions. We've got 16 bits of space
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// to play with so there can be quite a few pseudo
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// instructions.
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//0x04: loadall_or_reset_or_hang();
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0x4: decode IMMEDIATE {
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format BasicOperate {
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#if FULL_SYSTEM
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0x00: m5arm({{
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PseudoInst::arm(xc->tcBase());
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}}, IsNonSpeculative);
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0x01: m5quiesce({{
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PseudoInst::quiesce(xc->tcBase());
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}}, IsNonSpeculative);
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0x02: m5quiesceNs({{
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PseudoInst::quiesceNs(xc->tcBase(), Rdi);
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}}, IsNonSpeculative);
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0x03: m5quiesceCycle({{
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PseudoInst::quiesceCycles(xc->tcBase(), Rdi);
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}}, IsNonSpeculative);
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0x04: m5quiesceTime({{
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Rax = PseudoInst::quiesceTime(xc->tcBase());
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}}, IsNonSpeculative);
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#endif
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0x07: m5rpns({{
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Rax = PseudoInst::rpns(xc->tcBase());
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}}, IsNonSpeculative);
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0x21: m5exit({{
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PseudoInst::m5exit(xc->tcBase(), Rdi);
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}}, IsNonSpeculative);
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#if FULL_SYSTEM
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0x30: m5initparam({{
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Rax = xc->tcBase()->getCpuPtr()->
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system->init_param;
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}}, IsNonSpeculative);
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0x31: m5loadsymbol({{
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PseudoInst::loadsymbol(xc->tcBase());
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}}, IsNonSpeculative);
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#endif
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0x40: m5resetstats({{
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PseudoInst::resetstats(xc->tcBase(), Rdi, Rsi);
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}}, IsNonSpeculative);
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0x41: m5dumpstats({{
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PseudoInst::dumpstats(xc->tcBase(), Rdi, Rsi);
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}}, IsNonSpeculative);
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0x42: m5dumpresetstats({{
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PseudoInst::dumpresetstats(xc->tcBase(), Rdi, Rsi);
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}}, IsNonSpeculative);
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0x43: m5checkpoint({{
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PseudoInst::m5checkpoint(xc->tcBase(), Rdi, Rsi);
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}}, IsNonSpeculative);
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#if FULL_SYSTEM
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0x50: m5readfile({{
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Rax = PseudoInst::readfile(
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xc->tcBase(), Rdi, Rsi, Rdx);
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}}, IsNonSpeculative);
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#endif
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0x51: m5debugbreak({{
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PseudoInst::debugbreak(xc->tcBase());
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}}, IsNonSpeculative);
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0x52: m5switchcpu({{
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PseudoInst::switchcpu(xc->tcBase());
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}}, IsNonSpeculative);
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#if FULL_SYSTEM
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0x53: m5addsymbol({{
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PseudoInst::addsymbol(xc->tcBase(), Rdi, Rsi);
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}}, IsNonSpeculative);
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#endif
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0x54: m5panic({{
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panic("M5 panic instruction called at pc=%#x.\n",
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xc->readPC());
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}}, IsNonSpeculative);
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0x55: m5reserved1({{
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warn("M5 reserved opcode 1 ignored.\n");
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}}, IsNonSpeculative);
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0x56: m5reserved2({{
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warn("M5 reserved opcode 2 ignored.\n");
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}}, IsNonSpeculative);
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0x57: m5reserved3({{
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warn("M5 reserved opcode 3 ignored.\n");
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}}, IsNonSpeculative);
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0x58: m5reserved4({{
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warn("M5 reserved opcode 4 ignored.\n");
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}}, IsNonSpeculative);
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0x59: m5reserved5({{
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warn("M5 reserved opcode 5 ignored.\n");
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}}, IsNonSpeculative);
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default: Inst::UD2();
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}
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}
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#if FULL_SYSTEM
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0x05: syscall();
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#else
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@ -147,3 +147,11 @@ def template BasicDecode {{
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def template BasicDecodeWithMnemonic {{
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return new %(class_name)s("%(mnemonic)s", machInst);
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}};
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def format BasicOperate(code, *flags) {{
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iop = InstObjParams(name, Name, 'X86ISA::X86StaticInst', code, flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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@ -156,6 +156,7 @@ output exec {{
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#include "sim/sim_exit.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "sim/pseudo_inst.hh"
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using namespace X86ISA;
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using namespace std;
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@ -113,6 +113,10 @@ def operands {{
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'Rbx': ('IntReg', 'uqw', '(INTREG_RBX)', 'IsInteger', 13),
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'Rcx': ('IntReg', 'uqw', '(INTREG_RCX)', 'IsInteger', 14),
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'Rdx': ('IntReg', 'uqw', '(INTREG_RDX)', 'IsInteger', 15),
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'Rsp': ('IntReg', 'uqw', '(INTREG_RSP)', 'IsInteger', 16),
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'Rbp': ('IntReg', 'uqw', '(INTREG_RBP)', 'IsInteger', 17),
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'Rsi': ('IntReg', 'uqw', '(INTREG_RSI)', 'IsInteger', 18),
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'Rdi': ('IntReg', 'uqw', '(INTREG_RDI)', 'IsInteger', 19),
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'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20),
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'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21),
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'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22),
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@ -201,7 +201,7 @@ namespace X86ISA
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//For two byte instructions
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{ //LSB
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// MSB 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F
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/* 0 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY ,
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/* 0 */ 0 , 0 , 0 , 0 , WO, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY ,
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/* 0 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 2 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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/* 3 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
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