Automated merge with file:/home/stever/hg/m5-orig

--HG--
extra : convert_revision : 86a55cd98a9704f756a70aa0cbd2820cf92c821d

.hgignore

@@ -6,3 +6,4 @@ cscope.files
 cscope.out
 *.pyc
 *~
+.*.swp

src/arch/isa_specific.hh

@@ -49,6 +49,7 @@
 #define SPARC_ISA 42
 #define MIPS_ISA 34000
 #define X86_ISA 8086
+#define ARM_ISA 6
 
 //These tell the preprocessor where to find the files of a particular
 //ISA, and set the "TheISA" macro for use elsewhere.
@@ -60,6 +61,8 @@
     #define TheISA MipsISA
 #elif THE_ISA == X86_ISA
     #define TheISA X86ISA
+#elif THE_ISA == ARM_ISA
+    #define TheISA ArmISA
 #else
     #error "THE_ISA not set"
 #endif

src/arch/mips/regfile/misc_regfile.cc

@@ -577,7 +577,7 @@ MiscRegFile::CP0Event::process()
 }
 
 const char *
-MiscRegFile::CP0Event::description()
+MiscRegFile::CP0Event::description() const
 {
     return "Coprocessor-0 event";
 }

src/arch/mips/regfile/misc_regfile.hh

@@ -139,7 +139,7 @@ namespace MipsISA
             virtual void process();
 
             /** Returns the description of this event. */
-            const char *description();
+            const char *description() const;
 
             /** Schedule This Event */
             void scheduleEvent(int delay);

src/base/loader/elf_object.cc

@@ -88,6 +88,8 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data)
             arch = ObjectFile::X86;
         } else if (ehdr.e_ident[EI_CLASS] == ELFCLASS64) {
             arch = ObjectFile::Alpha;
+        } else if (ehdr.e_machine == EM_ARM) {
+            arch = ObjectFile::Arm;
         } else {
             warn("Unknown architecture: %d\n", ehdr.e_machine);
             arch = ObjectFile::UnknownArch;
@@ -98,6 +100,7 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data)
         {
 
           case ELFOSABI_LINUX:
+          case ELFOSABI_ARM:
             opSys = ObjectFile::Linux;
             break;
           case ELFOSABI_SOLARIS:

src/base/loader/object_file.hh

@@ -50,7 +50,8 @@ class ObjectFile
         SPARC64,
         SPARC32,
         Mips,
-        X86
+        X86,
+        Arm
     };
 
     enum OpSys {

src/cpu/BaseCPU.py

@@ -1,4 +1,4 @@
-# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# Copyright (c) 2005-2008 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -45,6 +45,8 @@ elif build_env['TARGET_ISA'] == 'x86':
     from X86TLB import X86DTB, X86ITB
 elif build_env['TARGET_ISA'] == 'mips':
     from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
+elif build_env['TARGET_ISA'] == 'arm':
+    from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB
 
 class BaseCPU(SimObject):
     type = 'BaseCPU'
@@ -76,6 +78,11 @@ class BaseCPU(SimObject):
         dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
         itb = Param.MipsITB(MipsITB(), "Instruction TLB")
         tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
+    elif build_env['TARGET_ISA'] == 'arm':
+        UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
+        dtb = Param.ArmDTB(ArmDTB(), "Data TLB")
+        itb = Param.ArmITB(ArmITB(), "Instruction TLB")
+        tlb = Param.ArmUTB(ArmUTB(), "Unified TLB")
     else:
         print "Don't know what TLB to use for ISA %s" % \
             build_env['TARGET_ISA']

src/cpu/base.cc

@@ -88,7 +88,7 @@ CPUProgressEvent::process()
 }
 
 const char *
-CPUProgressEvent::description()
+CPUProgressEvent::description() const
 {
     return "CPU Progress";
 }

src/cpu/base.hh

@@ -68,7 +68,7 @@ class CPUProgressEvent : public Event
 
     void process();
 
-    virtual const char *description();
+    virtual const char *description() const;
 };
 
 class BaseCPU : public MemObject

src/cpu/memtest/memtest.cc

@@ -39,12 +39,9 @@
 #include "base/misc.hh"
 #include "base/statistics.hh"
 #include "cpu/memtest/memtest.hh"
-//#include "cpu/simple_thread.hh"
-//#include "mem/cache/base_cache.hh"
 #include "mem/mem_object.hh"
 #include "mem/port.hh"
 #include "mem/packet.hh"
-//#include "mem/physical.hh"
 #include "mem/request.hh"
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"

src/cpu/memtest/memtest.hh

@@ -77,7 +77,7 @@ class MemTest : public MemObject
         TickEvent(MemTest *c)
             : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {}
         void process() {cpu->tick();}
-        virtual const char *description() { return "MemTest tick"; }
+        virtual const char *description() const { return "MemTest tick"; }
     };
 
     TickEvent tickEvent;

src/cpu/o3/commit.hh

@@ -97,7 +97,7 @@ class DefaultCommit
         TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid);
 
         void process();
-        const char *description();
+        const char *description() const;
     };
 
     /** Overall commit status. Used to determine if the CPU can deschedule

src/cpu/o3/commit_impl.hh

@@ -65,7 +65,7 @@ DefaultCommit<Impl>::TrapEvent::process()
 
 template <class Impl>
 const char *
-DefaultCommit<Impl>::TrapEvent::description()
+DefaultCommit<Impl>::TrapEvent::description() const
 {
     return "Trap";
 }

src/cpu/o3/cpu.cc

@@ -80,7 +80,7 @@ FullO3CPU<Impl>::TickEvent::process()
 
 template <class Impl>
 const char *
-FullO3CPU<Impl>::TickEvent::description()
+FullO3CPU<Impl>::TickEvent::description() const
 {
     return "FullO3CPU tick";
 }
@@ -109,7 +109,7 @@ FullO3CPU<Impl>::ActivateThreadEvent::process()
 
 template <class Impl>
 const char *
-FullO3CPU<Impl>::ActivateThreadEvent::description()
+FullO3CPU<Impl>::ActivateThreadEvent::description() const
 {
     return "FullO3CPU \"Activate Thread\"";
 }
@@ -141,7 +141,7 @@ FullO3CPU<Impl>::DeallocateContextEvent::process()
 
 template <class Impl>
 const char *
-FullO3CPU<Impl>::DeallocateContextEvent::description()
+FullO3CPU<Impl>::DeallocateContextEvent::description() const
 {
     return "FullO3CPU \"Deallocate Context\"";
 }

src/cpu/o3/cpu.hh

@@ -136,7 +136,7 @@ class FullO3CPU : public BaseO3CPU
         /** Processes a tick event, calling tick() on the CPU. */
         void process();
         /** Returns the description of the tick event. */
-        const char *description();
+        const char *description() const;
     };
 
     /** The tick event used for scheduling CPU ticks. */
@@ -178,7 +178,7 @@ class FullO3CPU : public BaseO3CPU
         void process();
 
         /** Returns the description of the event. */
-        const char *description();
+        const char *description() const;
     };
 
     /** Schedule thread to activate , regardless of its current state. */
@@ -229,7 +229,7 @@ class FullO3CPU : public BaseO3CPU
         void setRemove(bool _remove) { remove = _remove; }
 
         /** Returns the description of the event. */
-        const char *description();
+        const char *description() const;
     };
 
     /** Schedule cpu to deallocate thread context.*/

src/cpu/o3/dyn_inst.hh

@@ -49,6 +49,10 @@
     template <class Impl> class X86DynInst;
     struct X86SimpleImpl;
     typedef X86DynInst<X86SimpleImpl> O3DynInst;
+#elif THE_ISA == ARM_ISA
+    template <class Impl> class ArmDynInst;
+    struct ArmSimpleImpl;
+    typedef ArmDynInst<ArmSimpleImpl> O3DynInst;
 #else
     #error "O3DynInst not defined for this ISA"
 #endif

src/cpu/o3/inst_queue.hh

@@ -105,7 +105,7 @@ class InstructionQueue
                      InstructionQueue<Impl> *iq_ptr);
 
         virtual void process();
-        virtual const char *description();
+        virtual const char *description() const;
         void setFreeFU() { freeFU = true; }
     };
 

src/cpu/o3/inst_queue_impl.hh

@@ -58,7 +58,7 @@ InstructionQueue<Impl>::FUCompletion::process()
 
 template <class Impl>
 const char *
-InstructionQueue<Impl>::FUCompletion::description()
+InstructionQueue<Impl>::FUCompletion::description() const
 {
     return "Functional unit completion";
 }

src/cpu/o3/lsq_unit.hh

@@ -273,7 +273,7 @@ class LSQUnit {
         void process();
 
         /** Returns the description of this event. */
-        const char *description();
+        const char *description() const;
 
       private:
         /** Instruction whose results are being written back. */

src/cpu/o3/lsq_unit_impl.hh

@@ -67,7 +67,7 @@ LSQUnit<Impl>::WritebackEvent::process()
 
 template<class Impl>
 const char *
-LSQUnit<Impl>::WritebackEvent::description()
+LSQUnit<Impl>::WritebackEvent::description() const
 {
     return "Store writeback";
 }

src/cpu/ozone/back_end.hh

@@ -186,7 +186,7 @@ class BackEnd
         /** Processes writeback event. */
         virtual void process();
         /** Returns the description of the writeback event. */
-        virtual const char *description();
+        virtual const char *description() const;
     };
 
     BackEnd(Params *params);
@@ -309,7 +309,7 @@ class BackEnd
         DCacheCompletionEvent(BackEnd *_be);
 
         virtual void process();
-        virtual const char *description();
+        virtual const char *description() const;
     };
 
     friend class DCacheCompletionEvent;

src/cpu/ozone/back_end_impl.hh

@@ -581,7 +581,7 @@ BackEnd<Impl>::LdWritebackEvent::process()
 
 template<class Impl>
 const char *
-BackEnd<Impl>::LdWritebackEvent::description()
+BackEnd<Impl>::LdWritebackEvent::description() const
 {
     return "Load writeback";
 }
@@ -601,7 +601,7 @@ BackEnd<Impl>::DCacheCompletionEvent::process()
 
 template <class Impl>
 const char *
-BackEnd<Impl>::DCacheCompletionEvent::description()
+BackEnd<Impl>::DCacheCompletionEvent::description() const
 {
     return "Cache completion";
 }

src/cpu/ozone/cpu.hh

@@ -306,7 +306,7 @@ class OzoneCPU : public BaseCPU
 
         TickEvent(OzoneCPU *c, int w);
         void process();
-        const char *description();
+        const char *description() const;
     };
 
     TickEvent tickEvent;

src/cpu/ozone/cpu_impl.hh

@@ -82,7 +82,7 @@ OzoneCPU<Impl>::TickEvent::process()
 
 template <class Impl>
 const char *
-OzoneCPU<Impl>::TickEvent::description()
+OzoneCPU<Impl>::TickEvent::description() const
 {
     return "OzoneCPU tick";
 }

src/cpu/ozone/inorder_back_end.hh

@@ -161,7 +161,7 @@ class InorderBackEnd
         DCacheCompletionEvent(InorderBackEnd *_be);
 
         virtual void process();
-        virtual const char *description();
+        virtual const char *description() const;
 
         DynInstPtr inst;
     };

src/cpu/ozone/inorder_back_end_impl.hh

@@ -538,7 +538,7 @@ InorderBackEnd<Impl>::DCacheCompletionEvent::process()
 
 template <class Impl>
 const char *
-InorderBackEnd<Impl>::DCacheCompletionEvent::description()
+InorderBackEnd<Impl>::DCacheCompletionEvent::description() const
 {
     return "DCache completion";
 }

src/cpu/ozone/inst_queue.hh

@@ -99,7 +99,7 @@ class InstQueue
                      InstQueue<Impl> *iq_ptr);
 
         virtual void process();
-        virtual const char *description();
+        virtual const char *description() const;
     };
 #endif
     /** Constructs an IQ. */

src/cpu/ozone/inst_queue_impl.hh

@@ -62,7 +62,7 @@ InstQueue<Impl>::FUCompletion::process()
 
 template <class Impl>
 const char *
-InstQueue<Impl>::FUCompletion::description()
+InstQueue<Impl>::FUCompletion::description() const
 {
     return "Functional unit completion";
 }

src/cpu/ozone/lsq_unit.hh

@@ -80,7 +80,7 @@ class OzoneLSQ {
         void process();
 
         /** Returns the description of this event. */
-        const char *description();
+        const char *description() const;
 
       private:
         /** The store index of the store being written back. */

src/cpu/ozone/lsq_unit_impl.hh

@@ -60,7 +60,7 @@ OzoneLSQ<Impl>::StoreCompletionEvent::process()
 
 template <class Impl>
 const char *
-OzoneLSQ<Impl>::StoreCompletionEvent::description()
+OzoneLSQ<Impl>::StoreCompletionEvent::description() const
 {
     return "LSQ store completion";
 }

src/cpu/ozone/lw_back_end.hh

@@ -94,7 +94,7 @@ class LWBackEnd
         TrapEvent(LWBackEnd<Impl> *_be);
 
         void process();
-        const char *description();
+        const char *description() const;
     };
 
     LWBackEnd(Params *params);

src/cpu/ozone/lw_back_end_impl.hh

@@ -119,7 +119,7 @@ LWBackEnd<Impl>::TrapEvent::process()
 
 template <class Impl>
 const char *
-LWBackEnd<Impl>::TrapEvent::description()
+LWBackEnd<Impl>::TrapEvent::description() const
 {
     return "Trap";
 }

src/cpu/ozone/lw_lsq.hh

@@ -329,7 +329,7 @@ class OzoneLWLSQ {
         void process();
 
         /** Returns the description of this event. */
-        const char *description();
+        const char *description() const;
 
       private:
         /** Instruction whose results are being written back. */

src/cpu/ozone/lw_lsq_impl.hh

@@ -55,7 +55,7 @@ OzoneLWLSQ<Impl>::WritebackEvent::process()
 
 template<class Impl>
 const char *
-OzoneLWLSQ<Impl>::WritebackEvent::description()
+OzoneLWLSQ<Impl>::WritebackEvent::description() const
 {
     return "Store writeback";
 }

src/cpu/ozone/simple_cpu_builder.cc

@@ -35,7 +35,7 @@
 #include "cpu/ozone/cpu_impl.hh"
 #include "cpu/ozone/simple_impl.hh"
 #include "cpu/ozone/simple_params.hh"
-#include "mem/cache/base_cache.hh"
+#include "mem/cache/base.hh"
 #include "sim/SimpleOzoneCPU.hh"
 #include "sim/process.hh"
 #include "sim/sim_object.hh"

src/cpu/quiesce_event.cc

@@ -45,7 +45,7 @@ EndQuiesceEvent::process()
 }
 
 const char*
-EndQuiesceEvent::description()
+EndQuiesceEvent::description() const
 {
     return "End Quiesce";
 }

src/cpu/quiesce_event.hh

@@ -47,7 +47,7 @@ struct EndQuiesceEvent : public Event
     virtual void process();
 
     /** Event description */
-    virtual const char *description();
+    virtual const char *description() const;
 };
 
 #endif // __CPU_QUIESCE_EVENT_HH__

src/cpu/simple/atomic.cc

@@ -55,7 +55,7 @@ AtomicSimpleCPU::TickEvent::process()
 }
 
 const char *
-AtomicSimpleCPU::TickEvent::description()
+AtomicSimpleCPU::TickEvent::description() const
 {
     return "AtomicSimpleCPU tick";
 }

src/cpu/simple/atomic.hh

@@ -68,7 +68,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
         TickEvent(AtomicSimpleCPU *c);
         void process();
-        const char *description();
+        const char *description() const;
     };
 
     TickEvent tickEvent;

src/cpu/simple/timing.cc

@@ -598,13 +598,19 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
             assert(fault == NoFault);
         } else {
             if (fault == NoFault) {
+                // Note that ARM can have NULL packets if the instruction gets
+                // squashed due to predication
                 // early fail on store conditional: complete now
-                assert(dcache_pkt != NULL);
+                assert(dcache_pkt != NULL || THE_ISA == ARM_ISA);
+
                 fault = curStaticInst->completeAcc(dcache_pkt, this,
                                                    traceData);
-                delete dcache_pkt->req;
-                delete dcache_pkt;
-                dcache_pkt = NULL;
+                if (dcache_pkt != NULL)
+                {
+                    delete dcache_pkt->req;
+                    delete dcache_pkt;
+                    dcache_pkt = NULL;
+                }
 
                 // keep an instruction count
                 if (fault == NoFault)
@@ -816,7 +822,7 @@ TimingSimpleCPU::IprEvent::process()
 }
 
 const char *
-TimingSimpleCPU::IprEvent::description()
+TimingSimpleCPU::IprEvent::description() const
 {
     return "Timing Simple CPU Delay IPR event";
 }

src/cpu/simple/timing.hh

@@ -101,7 +101,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
             TickEvent(TimingSimpleCPU *_cpu)
                 :Event(&mainEventQueue), cpu(_cpu) {}
-            const char *description() { return "Timing CPU tick"; }
+            const char *description() const { return "Timing CPU tick"; }
             void schedule(PacketPtr _pkt, Tick t);
         };
 
@@ -127,7 +127,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
             ITickEvent(TimingSimpleCPU *_cpu)
                 : TickEvent(_cpu) {}
             void process();
-            const char *description() { return "Timing CPU icache tick"; }
+            const char *description() const { return "Timing CPU icache tick"; }
         };
 
         ITickEvent tickEvent;
@@ -155,7 +155,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
             DTickEvent(TimingSimpleCPU *_cpu)
                 : TickEvent(_cpu) {}
             void process();
-            const char *description() { return "Timing CPU dcache tick"; }
+            const char *description() const { return "Timing CPU dcache tick"; }
         };
 
         DTickEvent tickEvent;
@@ -219,7 +219,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
         TimingSimpleCPU *cpu;
         IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
         virtual void process();
-        virtual const char *description();
+        virtual const char *description() const;
     };
 
     void completeDrain();

src/cpu/static_inst.hh

@@ -259,6 +259,7 @@ class StaticInstBase : public RefCounted
     bool isMicroBranch() const { return flags[IsMicroBranch]; }
     //@}
 
+    void setLastMicroop() { flags[IsLastMicroop] = true; }
     /// Operation class.  Used to select appropriate function unit in issue.
     OpClass opClass()     const { return _opClass; }
 };

src/cpu/trace/opt_cpu.cc

@@ -204,7 +204,7 @@ OptCPU::TickEvent::process()
 }
 
 const char *
-OptCPU::TickEvent::description()
+OptCPU::TickEvent::description() const
 {
     return "OptCPU tick";
 }

src/cpu/trace/opt_cpu.hh

@@ -81,7 +81,7 @@ class OptCPU : public SimObject
         /**
          * Return a string description of this event.
          */
-        const char *description();
+        const char *description() const;
     };
 
     TickEvent tickEvent;

src/cpu/trace/trace_cpu.cc

@@ -129,7 +129,7 @@ TraceCompleteEvent::process()
 }
 
 const char *
-TraceCompleteEvent::description()
+TraceCompleteEvent::description() const
 {
     return "trace access complete";
 }
@@ -146,7 +146,7 @@ TraceCPU::TickEvent::process()
 }
 
 const char *
-TraceCPU::TickEvent::description()
+TraceCPU::TickEvent::description() const
 {
     return "TraceCPU tick";
 }

src/cpu/trace/trace_cpu.hh

@@ -93,7 +93,7 @@ class TraceCPU : public SimObject
         /**
          * Return a string description of this event.
          */
-        const char *description();
+        const char *description() const;
     };
 
     TickEvent tickEvent;
@@ -135,7 +135,7 @@ class TraceCompleteEvent : public Event
 
     void process();
 
-    virtual const char *description();
+    virtual const char *description() const;
 };
 
 #endif // __CPU_TRACE_TRACE_CPU_HH__

src/dev/alpha/tsunami_io.cc

@@ -205,7 +205,7 @@ TsunamiIO::RTC::RTCEvent::process()
 }
 
 const char *
-TsunamiIO::RTC::RTCEvent::description()
+TsunamiIO::RTC::RTCEvent::description() const
 {
     return "tsunami RTC interrupt";
 }
@@ -429,7 +429,7 @@ TsunamiIO::PITimer::Counter::CounterEvent::process()
 }
 
 const char *
-TsunamiIO::PITimer::Counter::CounterEvent::description()
+TsunamiIO::PITimer::Counter::CounterEvent::description() const
 {
     return "tsunami 8254 Interval timer";
 }

src/dev/alpha/tsunami_io.hh

@@ -73,7 +73,7 @@ class TsunamiIO : public BasicPioDevice
             virtual void process();
 
             /** Event description */
-            virtual const char *description();
+            virtual const char *description() const;
         };
 
       private:
@@ -161,7 +161,7 @@ class TsunamiIO : public BasicPioDevice
                 virtual void process();
 
                 /** Event description */
-                virtual const char *description();
+                virtual const char *description() const;
 
                 friend class Counter;
             };

src/dev/etherbus.hh

@@ -62,7 +62,8 @@ class EtherBus : public EtherObject
         DoneEvent(EventQueue *q, EtherBus *b)
             : Event(q), bus(b) {}
         virtual void process() { bus->txDone(); }
-        virtual const char *description() { return "ethernet bus completion"; }
+        virtual const char *description() const
+            { return "ethernet bus completion"; }
     };
 
     DoneEvent event;

src/dev/ethertap.hh

@@ -93,7 +93,8 @@ class EtherTap : public EtherObject
         TxEvent(EtherTap *_tap)
             : Event(&mainEventQueue), tap(_tap) {}
         void process() { tap->retransmit(); }
-        virtual const char *description() { return "EtherTap retransmit"; }
+        virtual const char *description() const
+            { return "EtherTap retransmit"; }
     };
 
     friend class TxEvent;

src/dev/i8254xGBe.cc

@@ -691,7 +691,7 @@ IGbE::RxDescCache::RxDescCache(IGbE *i, const std::string n, int s)
 {
 }
 
-bool
+void
 IGbE::RxDescCache::writePacket(EthPacketPtr packet)
 {
     // We shouldn't have to deal with any of these yet
@@ -707,7 +707,6 @@ IGbE::RxDescCache::writePacket(EthPacketPtr packet)
     pktDone = false;
     igbe->dmaWrite(igbe->platform->pciToDma(unusedCache.front()->buf),
             packet->length, &pktEvent, packet->data);
-    return true;
 }
 
 void
@@ -717,7 +716,6 @@ IGbE::RxDescCache::pktComplete()
     RxDesc *desc;
     desc = unusedCache.front();
 
-
     uint16_t crcfixup = igbe->regs.rctl.secrc() ? 0 : 4 ;
     desc->len = htole((uint16_t)(pktPtr->length + crcfixup));
     DPRINTF(EthernetDesc, "pktPtr->length: %d stripcrc offset: %d value written: %d %d\n",
@@ -938,6 +936,7 @@ IGbE::TxDescCache::pktComplete()
 
     DPRINTF(EthernetDesc, "DMA of packet complete\n");
 
+
     desc = unusedCache.front();
     assert((TxdOp::isLegacy(desc) || TxdOp::isData(desc)) && TxdOp::getLen(desc));
 
@@ -1215,6 +1214,7 @@ IGbE::txStateMachine()
             return;
         }
 
+
         int size;
         size = txDescCache.getPacketSize();
         if (size > 0 && txFifo.avail() > size) {
@@ -1261,6 +1261,7 @@ IGbE::ethRxPkt(EthPacketPtr pkt)
         postInterrupt(IT_RXO, true);
         return false;
     }
+
     return true;
 }
 
@@ -1290,6 +1291,8 @@ IGbE::rxStateMachine()
 
         if (descLeft == 0) {
             rxDescCache.writeback(0);
+            DPRINTF(EthernetSM, "RXS: No descriptors left in ring, forcing"
+                    " writeback and stopping ticking\n");
             rxTick = false;
         }
 
@@ -1342,16 +1345,14 @@ IGbE::rxStateMachine()
     EthPacketPtr pkt;
     pkt = rxFifo.front();
 
-    DPRINTF(EthernetSM, "RXS: Writing packet into memory\n");
-    if (rxDescCache.writePacket(pkt)) {
-        DPRINTF(EthernetSM, "RXS: Removing packet from FIFO\n");
-        rxFifo.pop();
-        DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n");
-        rxTick = false;
-        rxDmaPacket = true;
-        return;
-    }
 
+    rxDescCache.writePacket(pkt);
+    DPRINTF(EthernetSM, "RXS: Writing packet into memory\n");
+    DPRINTF(EthernetSM, "RXS: Removing packet from FIFO\n");
+    rxFifo.pop();
+    DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n");
+    rxTick = false;
+    rxDmaPacket = true;
 }
 
 void
@@ -1362,10 +1363,8 @@ IGbE::txWire()
         return;
     }
 
-    if (etherInt->askBusy()) {
-        // We'll get woken up when the packet ethTxDone() gets called
-        txFifoTick = false;
-    } else {
+
+    if (etherInt->sendPacket(txFifo.front())) {
         if (DTRACE(EthernetSM)) {
             IpPtr ip(txFifo.front());
             if (ip)
@@ -1374,13 +1373,12 @@ IGbE::txWire()
             else
                 DPRINTF(EthernetSM, "Transmitting Non-Ip packet\n");
         }
-
-        bool r = etherInt->sendPacket(txFifo.front());
-        assert(r);
-        r += 1;
         DPRINTF(EthernetSM, "TxFIFO: Successful transmit, bytes available in fifo: %d\n",
                 txFifo.avail());
         txFifo.pop();
+    } else {
+        // We'll get woken up when the packet ethTxDone() gets called
+        txFifoTick = false;
     }
 }
 

src/dev/i8254xGBe.hh

@@ -282,8 +282,12 @@ class IGbE : public EtherDevice
 
             wbOut = max_to_wb;
 
-            for (int x = 0; x < wbOut; x++)
-                memcpy(&wbBuf[x], usedCache[x], sizeof(T));
+            for (int x = 0; x < wbOut; x++) {
+                assert(usedCache.size());
+                memcpy(&wbBuf[x], usedCache[0], sizeof(T));
+                delete usedCache[0];
+                usedCache.pop_front();
+            }
 
 
             assert(wbOut);
@@ -298,13 +302,17 @@ class IGbE : public EtherDevice
         {
             size_t max_to_fetch;
 
+            if (curFetching)
+                return;
+
             if (descTail() >= cachePnt)
                 max_to_fetch = descTail() - cachePnt;
             else
                 max_to_fetch = descLen() - cachePnt;
 
-            max_to_fetch = std::min(max_to_fetch, (size - usedCache.size() -
-                        unusedCache.size()));
+            size_t free_cache = size - usedCache.size() - unusedCache.size();
+
+            max_to_fetch = std::min(max_to_fetch, free_cache);
 
             DPRINTF(EthernetDesc, "Fetching descriptors head: %d tail: "
                     "%d len: %d cachePnt: %d max_to_fetch: %d descleft: %d\n",
@@ -312,7 +320,7 @@ class IGbE : public EtherDevice
                     max_to_fetch, descLeft());
 
             // Nothing to do
-            if (max_to_fetch == 0 || curFetching)
+            if (max_to_fetch == 0)
                 return;
 
             // So we don't have two descriptor fetches going on at once
@@ -322,7 +330,6 @@ class IGbE : public EtherDevice
                     descBase() + cachePnt * sizeof(T),
                     igbe->platform->pciToDma(descBase() + cachePnt * sizeof(T)),
                     curFetching * sizeof(T));
-
             assert(curFetching);
             igbe->dmaRead(igbe->platform->pciToDma(descBase() + cachePnt * sizeof(T)),
                     curFetching * sizeof(T), &fetchEvent, (uint8_t*)fetchBuf);
@@ -369,11 +376,6 @@ class IGbE : public EtherDevice
 #ifndef NDEBUG
             long oldHead = curHead;
 #endif
-            for (int x = 0; x < wbOut; x++) {
-                assert(usedCache.size());
-                delete usedCache[0];
-                usedCache.pop_front();
-            };
 
             curHead += wbOut;
             wbOut = 0;
@@ -523,7 +525,7 @@ class IGbE : public EtherDevice
          * @param packet ethernet packet to write
          * @return if the packet could be written (there was a free descriptor)
          */
-        bool writePacket(EthPacketPtr packet);
+        void writePacket(EthPacketPtr packet);
         /** Called by event when dma to write packet is completed
          */
         void pktComplete();
@@ -553,9 +555,7 @@ class IGbE : public EtherDevice
         virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
         virtual void updateHead(long h) { igbe->regs.tdh(h); }
         virtual void enableSm();
-        virtual void intAfterWb() const {
-            igbe->postInterrupt(iGbReg::IT_TXDW);
-        }
+        virtual void intAfterWb() const { igbe->postInterrupt(iGbReg::IT_TXDW); }
         virtual void fetchAfterWb() {
             if (!igbe->txTick && igbe->getState() == SimObject::Running)
                 fetchDescriptors();

src/dev/mips/malta_io.cc

@@ -208,7 +208,7 @@ MaltaIO::RTC::RTCEvent::process()
 }
 
 const char *
-MaltaIO::RTC::RTCEvent::description()
+MaltaIO::RTC::RTCEvent::description() const
 {
     return "malta RTC interrupt";
 }
@@ -461,7 +461,7 @@ MaltaIO::PITimer::Counter::CounterEvent::process()
 }
 
 const char *
-MaltaIO::PITimer::Counter::CounterEvent::description()
+MaltaIO::PITimer::Counter::CounterEvent::description() const
 {
     return "malta 8254 Interval timer";
 }

src/dev/mips/malta_io.hh

@@ -79,7 +79,7 @@ class MaltaIO : public BasicPioDevice
             virtual void process();
 
             /** Event description */
-            virtual const char *description();
+            virtual const char *description() const;
         };
 
       private:
@@ -171,7 +171,7 @@ class MaltaIO : public BasicPioDevice
                 virtual void process();
 
                 /** Event description */
-                virtual const char *description();
+                virtual const char *description() const;
 
                 friend class Counter;
             };

src/dev/uart8250.cc

@@ -55,7 +55,7 @@ Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
 }
 
 const char *
-Uart8250::IntrEvent::description()
+Uart8250::IntrEvent::description() const
 {
     return "uart interrupt delay";
 }

src/dev/uart8250.hh

@@ -82,7 +82,7 @@ class Uart8250 : public Uart
         public:
             IntrEvent(Uart8250 *u, int bit);
             virtual void process();
-            virtual const char *description();
+            virtual const char *description() const;
             void scheduleIntr();
     };
 

src/mem/bridge.hh

@@ -150,7 +150,7 @@ class Bridge : public MemObject
 
             virtual void process() { port->trySend(); }
 
-            virtual const char *description() { return "bridge send"; }
+            virtual const char *description() const { return "bridge send"; }
         };
 
         SendEvent sendEvent;

src/mem/bus.cc

@@ -105,7 +105,7 @@ void Bus::BusFreeEvent::process()
     bus->recvRetry(-1);
 }
 
-const char * Bus::BusFreeEvent::description()
+const char * Bus::BusFreeEvent::description() const
 {
     return "bus became available";
 }
@@ -307,9 +307,10 @@ Bus::findPort(Addr addr)
     dest_id = checkPortCache(addr);
     if (dest_id == -1) {
         PortIter i = portMap.find(RangeSize(addr,1));
-        if (i != portMap.end())
-          dest_id = i->second;
-        updatePortCache(dest_id, i->first.start, i->first.end);
+        if (i != portMap.end()) {
+            dest_id = i->second;
+            updatePortCache(dest_id, i->first.start, i->first.end);
+        }
     }
 
     // Check if this matches the default range

src/mem/bus.hh

@@ -131,7 +131,7 @@ class Bus : public MemObject
       public:
         BusFreeEvent(Bus * _bus);
         void process();
-        const char *description();
+        const char *description() const;
     };
 
     /** a globally unique id for this bus. */

src/mem/cache/SConscript

@@ -32,10 +32,12 @@ Import('*')
 
 SimObject('BaseCache.py')
 
-Source('base_cache.cc')
+Source('base.cc')
 Source('cache.cc')
-Source('cache_blk.cc')
-Source('cache_builder.cc')
+Source('blk.cc')
+Source('builder.cc')
+Source('mshr.cc')
+Source('mshr_queue.cc')
 
 TraceFlag('Cache')
 TraceFlag('CachePort')

src/mem/cache/base.cc

@@ -35,8 +35,8 @@
 
 #include "cpu/base.hh"
 #include "cpu/smt.hh"
-#include "mem/cache/base_cache.hh"
-#include "mem/cache/miss/mshr.hh"
+#include "mem/cache/base.hh"
+#include "mem/cache/mshr.hh"
 
 using namespace std;
 

src/mem/cache/base.hh

@@ -47,7 +47,7 @@
 #include "base/misc.hh"
 #include "base/statistics.hh"
 #include "base/trace.hh"
-#include "mem/cache/miss/mshr_queue.hh"
+#include "mem/cache/mshr_queue.hh"
 #include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/tport.hh"

src/mem/cache/blk.cc

@@ -27,7 +27,7 @@
  */
 
 #include "base/cprintf.hh"
-#include "mem/cache/cache_blk.hh"
+#include "mem/cache/blk.hh"
 
 void
 CacheBlkPrintWrapper::print(std::ostream &os, int verbosity,

src/mem/cache/builder.cc

@@ -39,7 +39,7 @@
 #include "enums/Prefetch.hh"
 #include "mem/config/cache.hh"
 #include "mem/config/prefetch.hh"
-#include "mem/cache/base_cache.hh"
+#include "mem/cache/base.hh"
 #include "mem/cache/cache.hh"
 #include "mem/bus.hh"
 #include "params/BaseCache.hh"
@@ -67,13 +67,13 @@
 
 //Prefetcher Headers
 #if defined(USE_GHB)
-#include "mem/cache/prefetch/ghb_prefetcher.hh"
+#include "mem/cache/prefetch/ghb.hh"
 #endif
 #if defined(USE_TAGGED)
-#include "mem/cache/prefetch/tagged_prefetcher.hh"
+#include "mem/cache/prefetch/tagged.hh"
 #endif
 #if defined(USE_STRIDED)
-#include "mem/cache/prefetch/stride_prefetcher.hh"
+#include "mem/cache/prefetch/stride.hh"
 #endif
 
 

src/mem/cache/cache.hh

@@ -41,9 +41,9 @@
 
 #include "base/misc.hh" // fatal, panic, and warn
 
-#include "mem/cache/base_cache.hh"
-#include "mem/cache/cache_blk.hh"
-#include "mem/cache/miss/mshr.hh"
+#include "mem/cache/base.hh"
+#include "mem/cache/blk.hh"
+#include "mem/cache/mshr.hh"
 
 #include "sim/eventq.hh"
 

src/mem/cache/cache_impl.hh

@@ -42,9 +42,9 @@
 #include "base/range_ops.hh"
 
 #include "mem/cache/cache.hh"
-#include "mem/cache/cache_blk.hh"
-#include "mem/cache/miss/mshr.hh"
-#include "mem/cache/prefetch/base_prefetcher.hh"
+#include "mem/cache/blk.hh"
+#include "mem/cache/mshr.hh"
+#include "mem/cache/prefetch/base.hh"
 
 #include "sim/sim_exit.hh" // for SimExitEvent
 

src/mem/cache/mshr.cc

@@ -39,7 +39,7 @@
 #include <vector>
 #include <algorithm>
 
-#include "mem/cache/miss/mshr.hh"
+#include "mem/cache/mshr.hh"
 #include "sim/core.hh" // for curTick
 #include "sim/host.hh"
 #include "base/misc.hh"

src/mem/cache/mshr_queue.cc

@@ -32,7 +32,7 @@
  * Definition of MSHRQueue class functions.
  */
 
-#include "mem/cache/miss/mshr_queue.hh"
+#include "mem/cache/mshr_queue.hh"
 
 using namespace std;
 

src/mem/cache/mshr_queue.hh

@@ -38,7 +38,7 @@
 #include <vector>
 
 #include "mem/packet.hh"
-#include "mem/cache/miss/mshr.hh"
+#include "mem/cache/mshr.hh"
 
 /**
  * A Class for maintaining a list of pending and allocated memory requests.

src/mem/cache/prefetch/SConscript

@@ -30,8 +30,8 @@
 
 Import('*')
 
-Source('base_prefetcher.cc')
-Source('ghb_prefetcher.cc')
-Source('stride_prefetcher.cc')
-Source('tagged_prefetcher.cc')
+Source('base.cc')
+Source('ghb.cc')
+Source('stride.cc')
+Source('tagged.cc')
 

src/mem/cache/prefetch/base.cc

@@ -34,8 +34,8 @@
  */
 
 #include "base/trace.hh"
-#include "mem/cache/base_cache.hh"
-#include "mem/cache/prefetch/base_prefetcher.hh"
+#include "mem/cache/base.hh"
+#include "mem/cache/prefetch/base.hh"
 #include "mem/request.hh"
 #include <list>
 

src/mem/cache/prefetch/ghb.cc

@@ -34,7 +34,7 @@
  * GHB Prefetcher implementation.
  */
 
-#include "mem/cache/prefetch/ghb_prefetcher.hh"
+#include "mem/cache/prefetch/ghb.hh"
 #include "arch/isa_traits.hh"
 
 void

src/mem/cache/prefetch/ghb.hh

@@ -36,7 +36,7 @@
 #ifndef __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__
 #define __MEM_CACHE_PREFETCH_GHB_PREFETCHER_HH__
 
-#include "mem/cache/prefetch/base_prefetcher.hh"
+#include "mem/cache/prefetch/base.hh"
 
 class GHBPrefetcher : public BasePrefetcher
 {

src/mem/cache/prefetch/stride.cc

@@ -34,7 +34,7 @@
  * Stride Prefetcher template instantiations.
  */
 
-#include "mem/cache/prefetch/stride_prefetcher.hh"
+#include "mem/cache/prefetch/stride.hh"
 
 void
 StridePrefetcher::calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,

src/mem/cache/prefetch/stride.hh

@@ -36,7 +36,7 @@
 #ifndef __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
 #define __MEM_CACHE_PREFETCH_STRIDE_PREFETCHER_HH__
 
-#include "mem/cache/prefetch/base_prefetcher.hh"
+#include "mem/cache/prefetch/base.hh"
 
 class StridePrefetcher : public BasePrefetcher
 {

src/mem/cache/prefetch/tagged.cc

@@ -34,7 +34,7 @@
  */
 
 #include "arch/isa_traits.hh"
-#include "mem/cache/prefetch/tagged_prefetcher.hh"
+#include "mem/cache/prefetch/tagged.hh"
 
 TaggedPrefetcher::TaggedPrefetcher(const BaseCacheParams *p)
     : BasePrefetcher(p),

src/mem/cache/prefetch/tagged.hh

@@ -36,7 +36,7 @@
 #ifndef __MEM_CACHE_PREFETCH_TAGGED_PREFETCHER_HH__
 #define __MEM_CACHE_PREFETCH_TAGGED_PREFETCHER_HH__
 
-#include "mem/cache/prefetch/base_prefetcher.hh"
+#include "mem/cache/prefetch/base.hh"
 
 class TaggedPrefetcher : public BasePrefetcher
 {

src/mem/cache/tags/Repl.py

@@ -1,11 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-class Repl(SimObject):
-    type = 'Repl'
-    abstract = True
-
-class GenRepl(Repl):
-    type = 'GenRepl'
-    fresh_res = Param.Int("Fresh pool residency time")
-    num_pools = Param.Int("Number of priority pools")
-    pool_res = Param.Int("Pool residency time")

src/mem/cache/tags/SConscript

@@ -30,7 +30,7 @@
 
 Import('*')
 
-Source('base_tags.cc')
+Source('base.cc')
 Source('fa_lru.cc')
 Source('iic.cc')
 Source('lru.cc')
@@ -38,8 +38,8 @@ Source('split.cc')
 Source('split_lifo.cc')
 Source('split_lru.cc')
 
-SimObject('Repl.py')
-Source('repl/gen.cc')
+SimObject('iic_repl/Repl.py')
+Source('iic_repl/gen.cc')
 
 TraceFlag('IIC')
 TraceFlag('IICMore')

src/mem/cache/tags/base.cc

@@ -34,9 +34,9 @@
  * Definitions of BaseTags.
  */
 
-#include "mem/cache/tags/base_tags.hh"
+#include "mem/cache/tags/base.hh"
 
-#include "mem/cache/base_cache.hh"
+#include "mem/cache/base.hh"
 #include "cpu/smt.hh" //maxThreadsPerCPU
 #include "sim/sim_exit.hh"
 

src/mem/cache/tags/fa_lru.hh

@@ -38,10 +38,10 @@
 
 #include <list>
 
-#include "mem/cache/cache_blk.hh"
+#include "mem/cache/blk.hh"
 #include "mem/packet.hh"
 #include "base/hashmap.hh"
-#include "mem/cache/tags/base_tags.hh"
+#include "mem/cache/tags/base.hh"
 
 /**
  * A fully associative cache block.

src/mem/cache/tags/iic.cc

@@ -39,7 +39,7 @@
 
 #include <math.h>
 
-#include "mem/cache/base_cache.hh"
+#include "mem/cache/base.hh"
 #include "mem/cache/tags/iic.hh"
 #include "base/intmath.hh"
 #include "sim/core.hh" // for curTick

src/mem/cache/tags/iic.hh

@@ -39,11 +39,11 @@
 #include <list>
 #include <vector>
 
-#include "mem/cache/cache_blk.hh"
-#include "mem/cache/tags/repl/repl.hh"
+#include "mem/cache/blk.hh"
+#include "mem/cache/tags/iic_repl/repl.hh"
 #include "mem/packet.hh"
 #include "base/statistics.hh"
-#include "mem/cache/tags/base_tags.hh"
+#include "mem/cache/tags/base.hh"
 
 class BaseCache; // Forward declaration
 

src/mem/cache/tags/iic_repl/Repl.py

@@ -1,6 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2005-2008 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -28,7 +26,14 @@
 #
 # Authors: Nathan Binkert
 
-Import('*')
+from m5.SimObject import SimObject
+from m5.params import *
+class Repl(SimObject):
+    type = 'Repl'
+    abstract = True
 
-Source('mshr.cc')
-Source('mshr_queue.cc')
+class GenRepl(Repl):
+    type = 'GenRepl'
+    fresh_res = Param.Int("Fresh pool residency time")
+    num_pools = Param.Int("Number of priority pools")
+    pool_res = Param.Int("Pool residency time")

src/mem/cache/tags/iic_repl/gen.cc

@@ -38,7 +38,7 @@
 
 #include "base/misc.hh"
 #include "mem/cache/tags/iic.hh"
-#include "mem/cache/tags/repl/gen.hh"
+#include "mem/cache/tags/iic_repl/gen.hh"
 #include "params/GenRepl.hh"
 #include "sim/host.hh"
 

src/mem/cache/tags/iic_repl/gen.hh

@@ -39,7 +39,7 @@
 #include <list>
 
 #include "base/statistics.hh"
-#include "mem/cache/tags/repl/repl.hh"
+#include "mem/cache/tags/iic_repl/repl.hh"
 #include "params/GenRepl.hh"
 
 /**

src/mem/cache/tags/lru.cc

@@ -35,7 +35,7 @@
 
 #include <string>
 
-#include "mem/cache/base_cache.hh"
+#include "mem/cache/base.hh"
 #include "base/intmath.hh"
 #include "mem/cache/tags/lru.hh"
 #include "sim/core.hh"

src/mem/cache/tags/lru.hh

@@ -39,10 +39,10 @@
 #include <cstring>
 #include <list>
 
-#include "mem/cache/cache_blk.hh" // base class
+#include "mem/cache/blk.hh" // base class
 #include "mem/packet.hh" // for inlined functions
 #include <assert.h>
-#include "mem/cache/tags/base_tags.hh"
+#include "mem/cache/tags/base.hh"
 
 class BaseCache;
 

src/mem/cache/tags/split.cc

@@ -41,7 +41,7 @@
 #include "base/intmath.hh"
 #include "base/output.hh"
 #include "base/trace.hh"
-#include "mem/cache/base_cache.hh"
+#include "mem/cache/base.hh"
 #include "mem/cache/tags/split.hh"
 #include "mem/cache/tags/split_lifo.hh"
 #include "mem/cache/tags/split_lru.hh"

src/mem/cache/tags/split.hh

@@ -39,11 +39,11 @@
 #include <cstring>
 #include <list>
 
-#include "mem/cache/cache_blk.hh" // base class
+#include "mem/cache/blk.hh" // base class
 #include "mem/cache/tags/split_blk.hh"
 #include "mem/packet.hh" // for inlined functions
 #include <assert.h>
-#include "mem/cache/tags/base_tags.hh"
+#include "mem/cache/tags/base.hh"
 #include "base/hashmap.hh"
 
 class BaseCache;

src/mem/cache/tags/split_blk.hh

@@ -36,7 +36,7 @@
 #ifndef __SPLIT_BLK_HH__
 #define __SPLIT_BLK_HH__
 
-#include "mem/cache/cache_blk.hh" // base class
+#include "mem/cache/blk.hh" // base class
 
 /**
  * Split cache block.

src/mem/cache/tags/split_lifo.cc

@@ -35,7 +35,7 @@
 
 #include <string>
 
-#include "mem/cache/base_cache.hh"
+#include "mem/cache/base.hh"
 #include "base/intmath.hh"
 #include "mem/cache/tags/split_lifo.hh"
 #include "sim/core.hh"

src/mem/cache/tags/split_lifo.hh

@@ -39,12 +39,12 @@
 #include <cstring>
 #include <list>
 
-#include "mem/cache/cache_blk.hh" // base class
+#include "mem/cache/blk.hh" // base class
 #include "mem/cache/tags/split_blk.hh"
 #include "mem/packet.hh" // for inlined functions
 #include "base/hashmap.hh"
 #include <assert.h>
-#include "mem/cache/tags/base_tags.hh"
+#include "mem/cache/tags/base.hh"
 
 class BaseCache;
 

src/mem/cache/tags/split_lru.cc

@@ -35,7 +35,7 @@
 
 #include <string>
 
-#include "mem/cache/base_cache.hh"
+#include "mem/cache/base.hh"
 #include "base/intmath.hh"
 #include "mem/cache/tags/split_lru.hh"
 #include "sim/core.hh"

src/mem/cache/tags/split_lru.hh

@@ -39,11 +39,11 @@
 #include <cstring>
 #include <list>
 
-#include "mem/cache/cache_blk.hh" // base class
+#include "mem/cache/blk.hh" // base class
 #include "mem/cache/tags/split_blk.hh"
 #include "mem/packet.hh" // for inlined functions
 #include <assert.h>
-#include "mem/cache/tags/base_tags.hh"
+#include "mem/cache/tags/base.hh"
 
 class BaseCache;