sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

ARM: Decode 16 bit thumb immediate addressed memory instructions.

Browse source
This commit is contained in:
Gabe Black 2010-06-02 12:58:01 -05:00
parent 4bbd73649d
commit dc8af1b211
2 changed files with 53 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
src/arch/arm/isa/decoder/thumb.isa
View file

@ -92,18 +92,7 @@
0x2, 0x3: WarnUnimpl::ldr();
default: Thumb16MemReg::thumb16MemReg();
}
0x3: decode TOPCODE_12_11 {
0x0: WarnUnimpl::str(); //immediate, thumb
0x1: WarnUnimpl::ldr(); //immediate, thumb
0x2: WarnUnimpl::strb(); //immediate, thumb
0x3: WarnUnimpl::ldrb(); //immediate, thumb
}
0x4: decode TOPCODE_12_11 {
0x0: WarnUnimpl::strh(); //immediate, thumb
0x1: WarnUnimpl::ldrh(); //immediate, thumb
0x2: WarnUnimpl::str(); //immediate, thumb
0x3: WarnUnimpl::ldr(); //immediate, thumb
}
0x3, 0x4: Thumb16MemImm::thumb16MemImm();
0x5: decode TOPCODE_12_11 {
0x0: WarnUnimpl::adr();
0x1: WarnUnimpl::add(); //sp, immediate

52
src/arch/arm/isa/formats/mem.isa
View file

@ -398,6 +398,58 @@ def format Thumb16MemReg() {{
decode_block = decode % classNames
}};
def format Thumb16MemImm() {{
decode = '''
{
const uint32_t opa = bits(machInst, 15, 12);
const uint32_t opb = bits(machInst, 11, 9);
const uint32_t lrt = bits(machInst, 2, 0);
const uint32_t lrn = bits(machInst, 5, 3);
const uint32_t hrt = bits(machInst, 10, 8);
const uint32_t imm5 = bits(machInst, 10, 6);
const uint32_t imm8 = bits(machInst, 7, 0);
const bool load = bits(opb, 2);
switch (opa) {
case 0x6:
if (load) {
return new %(ldr)s(machInst, lrt, lrn, true, imm5 << 2);
} else {
return new %(str)s(machInst, lrt, lrn, true, imm5 << 2);
}
case 0x7:
if (load) {
return new %(ldrb)s(machInst, lrt, lrn, true, imm5);
} else {
return new %(strb)s(machInst, lrt, lrn, true, imm5);
}
case 0x8:
if (load) {
return new %(ldrh)s(machInst, lrt, lrn, true, imm5 << 1);
} else {
return new %(strh)s(machInst, lrt, lrn, true, imm5 << 1);
}
case 0x9:
if (load) {
return new %(ldr)s(machInst, hrt, INTREG_SP, true, imm8 << 2);
} else {
return new %(str)s(machInst, hrt, INTREG_SP, true, imm8 << 2);
}
default:
return new Unknown(machInst);
}
}
'''
classNames = {
"ldr" : loadImmClassName(False, True, False),
"str" : storeImmClassName(False, True, False),
"ldrh" : loadImmClassName(False, True, False, size=2),
"strh" : storeImmClassName(False, True, False, size=2),
"ldrb" : loadImmClassName(False, True, False, size=1),
"strb" : storeImmClassName(False, True, False, size=1),
}
decode_block = decode % classNames
}};
def format ArmLoadMemory(memacc_code, ea_code = {{ EA = Rn + disp; }},
mem_flags = [], inst_flags = []) {{
ea_code = ArmGenericCodeSubs(ea_code)