sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

X86: Use atCPL0 for accesses that are part of CPU machinery.

Browse source
This commit is contained in:
Gabe Black 2009-02-25 10:18:29 -08:00
parent dc53ca89f6
commit ba69184630
1 changed files with 10 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
src/arch/x86/isa/insts/romutil.py
View file

@ -40,8 +40,8 @@ def rom
# Load the gate descriptor from the IDT
slli t4, t1, 4, dataSize=8
ld t2, idtr, [1, t0, t4], 8, dataSize=8, addressSize=8
ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8
ld t2, idtr, [1, t0, t4], 8, dataSize=8, addressSize=8, atCPL0=True
ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8, atCPL0=True
# Make sure the descriptor is a legal gate.
chks t1, t4, %(gateCheckType)s
@ -54,10 +54,10 @@ def rom
andi t5, t10, 0xF8, dataSize=8
andi t0, t10, 0x4, flags=(EZF,), dataSize=2
br rom_local_label("%(startLabel)s_globalDescriptor"), flags=(CEZF,)
ld t3, tsl, [1, t0, t5], dataSize=8, addressSize=8
ld t3, tsl, [1, t0, t5], dataSize=8, addressSize=8, atCPL0=True
br rom_local_label("%(startLabel)s_processDescriptor")
%(startLabel)s_globalDescriptor:
ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8
ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8, atCPL0=True
%(startLabel)s_processDescriptor:
chks t10, t3, IntCSCheck, dataSize=8
wrdl hs, t3, t10, dataSize=8
@ -104,18 +104,13 @@ def rom
%(startLabel)s_cplStackSwitch:
# Get the new rsp from the TSS
ld t6, tr, [8, t10, t0], 4, dataSize=8, addressSize=8
ld t6, tr, [8, t10, t0], 4, dataSize=8, addressSize=8, atCPL0=True
%(startLabel)s_stackSwitched:
andi t6, t6, 0xF0, dataSize=1
subi t6, t6, 40 + %(errorCodeSize)d, dataSize=8
# Check that we can access everything we need to on the stack
ldst t0, hs, [1, t0, t6], dataSize=8, addressSize=8
ldst t0, hs, [1, t0, t6], \
32 + %(errorCodeSize)d, dataSize=8, addressSize=8
##
## Point of no return.
## We're now going to irrevocably modify visible state.
@ -136,6 +131,11 @@ def rom
rdsel t10, cs, dataSize=2
wrsel cs, t5, dataSize=2
# Check that we can access everything we need to on the stack
ldst t0, hs, [1, t0, t6], dataSize=8, addressSize=8
ldst t0, hs, [1, t0, t6], \
32 + %(errorCodeSize)d, dataSize=8, addressSize=8
#
# Build up the interrupt stack frame