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X86: Make the segment register reading microops use merge.

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Gabe Black 2009-02-25 10:20:47 -08:00
parent 28efb3c6e3
commit b035c917a5
2 changed files with 5 additions and 5 deletions
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2
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
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@ -142,7 +142,7 @@ processCSDescriptor:
# Here, we know we're -not- in 64 bit mode, so we should do the
# appropriate/other RIP checks.
# if temp_RIP > CS.limit throw #GP(0)
rdlimit t6, cs
rdlimit t6, cs, dataSize=8
subi t0, t1, t6, flags=(ECF,)
fault "new GeneralProtection(0)", flags=(CECF,)

8
src/arch/x86/isa/microops/regop.isa
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@ -1052,22 +1052,22 @@ let {{
class Rdbase(SegOp):
code = '''
DestReg = SegBaseSrc1;
DestReg = merge(DestReg, SegBaseSrc1, dataSize);
'''
class Rdlimit(SegOp):
code = '''
DestReg = SegLimitSrc1;
DestReg = merge(DestReg, SegLimitSrc1, dataSize);
'''
class RdAttr(SegOp):
code = '''
DestReg = SegAttrSrc1;
DestReg = merge(DestReg, SegAttrSrc1, dataSize);
'''
class Rdsel(SegOp):
code = '''
DestReg = SegSelSrc1;
DestReg = merge(DestReg, SegSelSrc1, dataSize);
'''
class Rdval(RegOp):