From b035c917a5e0749cb4068d2de66331beda52d222 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 25 Feb 2009 10:20:47 -0800 Subject: [PATCH] X86: Make the segment register reading microops use merge. --- .../control_transfer/interrupts_and_exceptions.py | 2 +- src/arch/x86/isa/microops/regop.isa | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py index 8d66cc445..8203f7c2c 100644 --- a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py @@ -142,7 +142,7 @@ processCSDescriptor: # Here, we know we're -not- in 64 bit mode, so we should do the # appropriate/other RIP checks. # if temp_RIP > CS.limit throw #GP(0) - rdlimit t6, cs + rdlimit t6, cs, dataSize=8 subi t0, t1, t6, flags=(ECF,) fault "new GeneralProtection(0)", flags=(CECF,) diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index fd2a3a64f..1349a64c2 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -1052,22 +1052,22 @@ let {{ class Rdbase(SegOp): code = ''' - DestReg = SegBaseSrc1; + DestReg = merge(DestReg, SegBaseSrc1, dataSize); ''' class Rdlimit(SegOp): code = ''' - DestReg = SegLimitSrc1; + DestReg = merge(DestReg, SegLimitSrc1, dataSize); ''' class RdAttr(SegOp): code = ''' - DestReg = SegAttrSrc1; + DestReg = merge(DestReg, SegAttrSrc1, dataSize); ''' class Rdsel(SegOp): code = ''' - DestReg = SegSelSrc1; + DestReg = merge(DestReg, SegSelSrc1, dataSize); ''' class Rdval(RegOp):