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X86: Make the qaud width bswap instruction handle the fact that 32 bit operations zero extend.

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This commit is contained in:
Gabe Black 2009-08-07 10:12:58 -07:00
parent 0526f453aa
commit 62a2e85c9a
1 changed files with 10 additions and 10 deletions
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20
src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py
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@ -64,15 +64,15 @@ def macroop BSWAP_D_R
def macroop BSWAP_Q_R
{
roli reg, reg, 8, dataSize=2
roli reg, reg, 16, dataSize=4
roli reg, reg, 8, dataSize=2
roli reg, reg, 32, dataSize=8
roli reg, reg, 8, dataSize=2
roli reg, reg, 16, dataSize=4
roli reg, reg, 8, dataSize=2
roli t1, reg, 16, dataSize=4
# Top 4 bytes of t1 are now zero
roli t1, t1, 8, dataSize=2
roli t1, t1, 32, dataSize=8
srli t2, reg, 32, dataSize=8
roli t2, t2, 8, dataSize=2
roli t2, t2, 16, dataSize=4
# Top 4 bytes of t2 are now zero
roli t2, t2, 8, dataSize=2
or reg, t1, t2, dataSize=8
};
'''
#let {{
# class BSWAP(Inst):
# "GenFault ${new UnimpInstFault}"
#}};