ARM: Make inst bitfields accessible outside of the isa desc.
This commit is contained in:
Gabe Black
parent
47e71d674a
commit
d1d733f636
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@ -34,135 +34,135 @@
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//
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// Opcode fields
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def bitfield OPCODE <27:25>;
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def bitfield OPCODE_27_25 <27:25>;
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def bitfield OPCODE_24_21 <24:21>;
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def bitfield OPCODE_24_23 <24:23>;
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def bitfield OPCODE_24 <24:24>;
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def bitfield OPCODE_23_20 <23:20>;
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def bitfield OPCODE_23_21 <23:21>;
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def bitfield OPCODE_23 <23:23>;
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def bitfield OPCODE_22_8 <22: 8>;
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def bitfield OPCODE_22_21 <22:21>;
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def bitfield OPCODE_22 <22:22>;
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def bitfield OPCODE_21_20 <21:20>;
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def bitfield OPCODE_20 <20:20>;
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def bitfield OPCODE_19_18 <19:18>;
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def bitfield OPCODE_19 <19:19>;
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def bitfield OPCODE_15_12 <15:12>;
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def bitfield OPCODE_15 <15:15>;
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def bitfield OPCODE_9 < 9: 9>;
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def bitfield OPCODE_7_4 < 7: 4>;
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def bitfield OPCODE_7_5 < 7: 5>;
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def bitfield OPCODE_7_6 < 7: 6>;
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def bitfield OPCODE_7 < 7: 7>;
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def bitfield OPCODE_6_5 < 6: 5>;
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def bitfield OPCODE_6 < 6: 6>;
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def bitfield OPCODE_5 < 5: 5>;
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def bitfield OPCODE_4 < 4: 4>;
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def bitfield OPCODE opcode;
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def bitfield OPCODE_27_25 opcode27_25;
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def bitfield OPCODE_24_21 opcode24_21;
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def bitfield OPCODE_24_23 opcode24_23;
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def bitfield OPCODE_24 opcode24;
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def bitfield OPCODE_23_20 opcode23_20;
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def bitfield OPCODE_23_21 opcode23_21;
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def bitfield OPCODE_23 opcode23;
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def bitfield OPCODE_22_8 opcode22_8;
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def bitfield OPCODE_22_21 opcode22_21;
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def bitfield OPCODE_22 opcode22;
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def bitfield OPCODE_21_20 opcode21_20;
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def bitfield OPCODE_20 opcode20;
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def bitfield OPCODE_19_18 opcode19_18;
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def bitfield OPCODE_19 opcode19;
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def bitfield OPCODE_15_12 opcode15_12;
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def bitfield OPCODE_15 opcode15;
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def bitfield OPCODE_9 opcode9;
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def bitfield OPCODE_7_4 opcode7_4;
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def bitfield OPCODE_7_5 opcode7_5;
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def bitfield OPCODE_7_6 opcode7_6;
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def bitfield OPCODE_7 opcode7;
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def bitfield OPCODE_6_5 opcode6_5;
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def bitfield OPCODE_6 opcode6;
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def bitfield OPCODE_5 opcode5;
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def bitfield OPCODE_4 opcode4;
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// Other
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def bitfield COND_CODE <31:28>;
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def bitfield S_FIELD <20:20>;
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def bitfield RN <19:16>;
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def bitfield RD <15:12>;
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def bitfield SHIFT_SIZE <11: 7>;
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def bitfield SHIFT < 6: 5>;
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def bitfield RM < 3: 0>;
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def bitfield COND_CODE condCode;
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def bitfield S_FIELD sField;
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def bitfield RN rn;
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def bitfield RD rd;
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def bitfield SHIFT_SIZE shiftSize;
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def bitfield SHIFT shift;
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def bitfield RM rm;
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def bitfield RS <11: 8>;
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def bitfield RS rs;
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def bitfield RDUP <19:16>;
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def bitfield RNDN <15:12>;
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def bitfield RDUP rdup;
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def bitfield RNDN rddn;
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def bitfield RDHI <15:12>;
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def bitfield RDLO <11: 8>;
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def bitfield RDHI rdhi;
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def bitfield RDLO rdlo;
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def bitfield U_FIELD <23:23>;
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def bitfield U_FIELD uField;
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def bitfield PUSWL <24:20>;
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def bitfield PREPOST <24:24>;
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def bitfield UP <23:23>;
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def bitfield PSRUSER <22:22>;
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def bitfield WRITEBACK <21:21>;
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def bitfield LOADOP <20:20>;
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def bitfield PUSWL puswl;
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def bitfield PREPOST puswl.prepost;
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def bitfield UP puswl.up;
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def bitfield PSRUSER puswl.psruser;
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def bitfield WRITEBACK puswl.writeback;
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def bitfield LOADOP puswl.loadOp;
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def bitfield PUBWL <24:20>;
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def bitfield PUIWL <24:20>;
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def bitfield BYTEACCESS <22:22>;
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def bitfield PUBWL pubwl;
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def bitfield PUIWL puiwl;
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def bitfield BYTEACCESS byteAccess;
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def bitfield LUAS <23:20>;
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def bitfield LUAS luas;
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def bitfield IMM < 7: 0>;
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def bitfield IMMED_7_4 < 7: 4>;
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def bitfield IMMED_3_0 < 3: 0>;
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def bitfield IMM imm;
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def bitfield IMMED_7_4 immed7_4;
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def bitfield IMMED_3_0 immed3_0;
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def bitfield F_MSR <19:19>;
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def bitfield S_MSR <18:18>;
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def bitfield X_MSR <17:17>;
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def bitfield C_MSR <16:16>;
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def bitfield F_MSR msr.f;
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def bitfield S_MSR msr.s;
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def bitfield X_MSR msr.x;
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def bitfield C_MSR msr.c;
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def bitfield Y_6 < 6: 6>;
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def bitfield X_5 < 5: 5>;
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def bitfield Y_6 y;
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def bitfield X_5 x;
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def bitfield IMMED_15_4 <15: 4>;
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def bitfield IMMED_15_4 immed15_4;
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def bitfield W_FIELD <21:21>;
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def bitfield W_FIELD wField;
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def bitfield ROTATE <11: 8>;
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def bitfield IMMED_7_0 < 7: 0>;
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def bitfield ROTATE rotate;
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def bitfield IMMED_7_0 immed7_0;
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def bitfield T_FIELD <21:21>;
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def bitfield IMMED_11_0 <11: 0>;
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def bitfield T_FIELD tField;
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def bitfield IMMED_11_0 immed11_0;
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def bitfield IMMED_20_16 <20:16>;
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def bitfield IMMED_19_16 <19:16>;
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def bitfield IMMED_20_16 immed20_16;
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def bitfield IMMED_19_16 immed19_16;
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def bitfield IMMED_HI_11_8 <11: 8>;
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def bitfield IMMED_LO_3_0 < 3: 0>;
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def bitfield IMMED_HI_11_8 immedHi11_8;
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def bitfield IMMED_LO_3_0 immedLo3_0;
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def bitfield ROT <11:10>;
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def bitfield ROT rot;
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def bitfield R_FIELD < 5: 5>;
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def bitfield R_FIELD rField;
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def bitfield CARET <22:22>;
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def bitfield REGLIST <15: 0>;
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def bitfield CARET caret;
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def bitfield REGLIST regList;
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def bitfield OFFSET <23: 0>;
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def bitfield COPRO <11: 8>;
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def bitfield OP1_7_4 < 7: 4>;
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def bitfield CM < 3: 0>;
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def bitfield OFFSET offset;
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def bitfield COPRO copro;
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def bitfield OP1_7_4 op1_7_4;
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def bitfield CM cm;
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def bitfield L_FIELD <22:22>;
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def bitfield CD <15:12>;
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def bitfield OPTION < 7: 0>;
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def bitfield L_FIELD lField;
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def bitfield CD cd;
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def bitfield OPTION option;
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def bitfield OP1_23_20 <23:20>;
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def bitfield CN <19:16>;
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def bitfield OP2_7_5 < 7: 5>;
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def bitfield OP1_23_20 op1_23_20;
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def bitfield CN cn;
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def bitfield OP2_7_5 op2_7_5;
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def bitfield OP1_23_21 <23:21>;
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def bitfield OP1_23_21 op1_23_21;
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def bitfield IMMED_23_0 <23: 0>;
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def bitfield M_FIELD <17:17>;
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def bitfield A_FIELD < 8: 8>;
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def bitfield I_FIELD < 7: 7>;
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def bitfield F_FIELD < 6: 6>;
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def bitfield MODE < 4: 0>;
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def bitfield IMMED_23_0 immed23_0;
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def bitfield M_FIELD mField;
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def bitfield A_FIELD aField;
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def bitfield I_FIELD iField;
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def bitfield F_FIELD fField;
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def bitfield MODE mode;
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def bitfield A_BLX <24:24>;
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def bitfield A_BLX aBlx;
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def bitfield CPNUM <11: 8>;
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def bitfield CPNUM cpNum;
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// Note that FP Regs are only 3 bits
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def bitfield FN <18:16>;
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def bitfield FD <14:12>;
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def bitfield FPREGIMM < 3: 3>;
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def bitfield FN fn;
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def bitfield FD fd;
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def bitfield FPREGIMM fpRegImm;
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// We can just use 3:0 for FM since the hard-wired FP regs are handled in
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// float_regfile.hh
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def bitfield FM < 3: 0>;
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def bitfield FPIMM < 2: 0>;
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def bitfield PUNWL <24:20>;
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def bitfield FM fm;
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def bitfield FPIMM fpImm;
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def bitfield PUNWL punwl;
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// M5 instructions
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def bitfield M5FUNC <7:0>;
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def bitfield M5FUNC m5Func;
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@ -55,7 +55,7 @@ output header {{
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/// Constructor
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PredOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
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ArmStaticInst(mnem, _machInst, __opClass),
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condCode((ArmISA::ConditionCode)COND_CODE)
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condCode((ArmISA::ConditionCode)(unsigned)COND_CODE)
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{
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}
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@ -31,12 +31,147 @@
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#ifndef __ARCH_ARM_TYPES_HH__
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#define __ARCH_ARM_TYPES_HH__
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#include "base/bitunion.hh"
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#include "base/types.hh"
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namespace ArmISA
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{
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typedef uint32_t MachInst;
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typedef uint64_t ExtMachInst;
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BitUnion32(ExtMachInst)
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// All the different types of opcode fields.
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Bitfield<27, 25> opcode;
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Bitfield<27, 25> opcode27_25;
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Bitfield<24, 21> opcode24_21;
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Bitfield<24, 23> opcode24_23;
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Bitfield<24> opcode24;
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Bitfield<23, 20> opcode23_20;
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Bitfield<23, 21> opcode23_21;
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Bitfield<23> opcode23;
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Bitfield<22, 8> opcode22_8;
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Bitfield<22, 21> opcode22_21;
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Bitfield<22> opcode22;
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Bitfield<21, 20> opcode21_20;
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Bitfield<20> opcode20;
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Bitfield<19, 18> opcode19_18;
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Bitfield<19> opcode19;
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Bitfield<15, 12> opcode15_12;
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Bitfield<15> opcode15;
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Bitfield<9> opcode9;
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Bitfield<7, 4> opcode7_4;
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Bitfield<7, 5> opcode7_5;
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Bitfield<7, 6> opcode7_6;
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Bitfield<7> opcode7;
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Bitfield<6, 5> opcode6_5;
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Bitfield<6> opcode6;
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Bitfield<5> opcode5;
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Bitfield<4> opcode4;
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Bitfield<31, 28> condCode;
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Bitfield<20> sField;
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Bitfield<19, 16> rn;
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Bitfield<15, 12> rd;
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Bitfield<11, 7> shiftSize;
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Bitfield<6, 5> shift;
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Bitfield<3, 0> rm;
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Bitfield<11, 8> rs;
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Bitfield<19, 16> rdup;
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Bitfield<15, 12> rddn;
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Bitfield<15, 12> rdhi;
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Bitfield<11, 8> rdlo;
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Bitfield<23> uField;
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SubBitUnion(puswl, 24, 20)
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Bitfield<24> prepost;
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Bitfield<23> up;
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Bitfield<22> psruser;
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Bitfield<21> writeback;
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Bitfield<20> loadOp;
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EndSubBitUnion(puswl)
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Bitfield<24, 20> pubwl;
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Bitfield<24, 20> puiwl;
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Bitfield<22> byteAccess;
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Bitfield<23, 20> luas;
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SubBitUnion(imm, 7, 0)
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Bitfield<7, 4> imm7_4;
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Bitfield<3, 0> imm3_0;
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EndSubBitUnion(imm)
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SubBitUnion(msr, 19, 16)
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Bitfield<19> f;
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Bitfield<18> s;
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Bitfield<17> x;
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Bitfield<16> c;
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EndSubBitUnion(msr)
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Bitfield<6> y;
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Bitfield<5> x;
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Bitfield<15, 4> immed15_4;
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Bitfield<21> wField;
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Bitfield<11, 8> rotate;
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Bitfield<7, 0> immed7_0;
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Bitfield<21> tField;
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Bitfield<11, 0> immed11_0;
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Bitfield<20, 16> immed20_16;
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Bitfield<19, 16> immed19_16;
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Bitfield<11, 8> immedHi11_8;
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Bitfield<3, 0> immedLo3_0;
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Bitfield<11, 10> rot;
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Bitfield<5> rField;
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Bitfield<22> caret;
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Bitfield<15, 0> regList;
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Bitfield<23, 0> offset;
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Bitfield<11, 8> copro;
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Bitfield<7, 4> op1_7_4;
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Bitfield<3, 0> cm;
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Bitfield<22> lField;
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Bitfield<15, 12> cd;
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Bitfield<7, 0> option;
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Bitfield<23, 20> op1_23_20;
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Bitfield<19, 16> cn;
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Bitfield<7, 5> op2_7_5;
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Bitfield<23, 21> op1_23_21;
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Bitfield<23, 0> immed23_0;
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Bitfield<17> mField;
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Bitfield<8> aField;
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Bitfield<7> iField;
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Bitfield<6> fField;
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Bitfield<4, 0> mode;
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Bitfield<24> aBlx;
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Bitfield<11, 8> cpNum;
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Bitfield<18, 16> fn;
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Bitfield<14, 12> fd;
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Bitfield<3> fpRegImm;
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Bitfield<3, 0> fm;
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Bitfield<2, 0> fpImm;
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Bitfield<24, 20> punwl;
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Bitfield<7, 0> m5Func;
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EndBitUnion(ExtMachInst)
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typedef uint8_t RegIndex;
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typedef uint64_t IntReg;
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@ -35,9 +35,19 @@
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#include "arch/arm/miscregs.hh"
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#include "arch/arm/types.hh"
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#include "base/hashmap.hh"
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#include "base/types.hh"
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#include "cpu/thread_context.hh"
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namespace __hash_namespace {
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template<>
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struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
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size_t operator()(const ArmISA::ExtMachInst &emi) const {
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return hash<uint32_t>::operator()((uint32_t)emi);
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};
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};
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}
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namespace ArmISA {
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inline bool
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