ARM: Add support for "SUBS PC, LR and related instructions".
This commit is contained in:
Gabe Black
parent
2419903dc0
commit
aa45fafb2e
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@ -192,8 +192,11 @@ def format Thumb32BranchesAndMiscCtrl() {{
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case 0x3c:
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return new WarnUnimplemented("bxj", machInst);
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case 0x3d:
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return new WarnUnimplemented("subs_pc_lr_and_rel_insts",
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machInst);
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{
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const uint32_t imm32 = bits(machInst, 7, 0);
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return new SubsImmPclr(machInst, INTREG_PC, INTREG_LR,
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imm32, false);
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}
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case 0x3e:
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case 0x3f:
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return new WarnUnimplemented("mrs", machInst);
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@ -36,12 +36,21 @@
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// Authors: Gabe Black
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def format ArmDataProcReg() {{
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pclr = '''
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return new %(className)ssRegPclr(machInst, %(dest)s,
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%(op1)s, rm, imm5,
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type);
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'''
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instDecode = '''
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case %(opcode)#x:
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if (immShift) {
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if (setCc) {
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return new %(className)sRegCc(machInst, %(dest)s, %(op1)s,
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rm, imm5, type);
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if (%(dest)s == INTREG_PC) {
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%(pclr)s
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} else {
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return new %(className)sRegCc(machInst, %(dest)s,
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%(op1)s, rm, imm5, type);
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}
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} else {
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return new %(className)sReg(machInst, %(dest)s, %(op1)s,
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rm, imm5, type);
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@ -58,12 +67,26 @@ def format ArmDataProcReg() {{
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break;
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'''
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def instCode(opcode, mnem, dest="rd", op1="rn"):
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global instDecode
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return instDecode % { "className": mnem.capitalize(),
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"opcode": opcode,
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"dest": dest,
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"op1": op1 }
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def instCode(opcode, mnem, useDest = True, useOp1 = True):
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global pclr
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if useDest:
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dest = "rd"
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else:
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dest = "INTREG_ZERO"
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if useOp1:
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op1 = "rn"
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else:
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op1 = "INTREG_ZERO"
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global instDecode, pclrCode
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substDict = { "className": mnem.capitalize(),
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"opcode": opcode,
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"dest": dest,
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"op1": op1 }
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if useDest:
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substDict["pclr"] = pclr % substDict
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else:
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substDict["pclr"] = ""
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return instDecode % substDict
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decode_block = '''
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{
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@ -85,14 +108,14 @@ def format ArmDataProcReg() {{
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decode_block += instCode(0x5, "adc")
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decode_block += instCode(0x6, "sbc")
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decode_block += instCode(0x7, "rsc")
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decode_block += instCode(0x8, "tst", dest="INTREG_ZERO")
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decode_block += instCode(0x9, "teq", dest="INTREG_ZERO")
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decode_block += instCode(0xa, "cmp", dest="INTREG_ZERO")
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decode_block += instCode(0xb, "cmn", dest="INTREG_ZERO")
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decode_block += instCode(0x8, "tst", useDest = False)
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decode_block += instCode(0x9, "teq", useDest = False)
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decode_block += instCode(0xa, "cmp", useDest = False)
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decode_block += instCode(0xb, "cmn", useDest = False)
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decode_block += instCode(0xc, "orr")
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decode_block += instCode(0xd, "mov", op1="INTREG_ZERO")
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decode_block += instCode(0xd, "mov", useOp1 = False)
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decode_block += instCode(0xe, "bic")
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decode_block += instCode(0xf, "mvn", op1="INTREG_ZERO")
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decode_block += instCode(0xf, "mvn", useOp1 = False)
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decode_block += '''
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default:
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return new Unknown(machInst);
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@ -102,43 +125,70 @@ def format ArmDataProcReg() {{
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}};
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def format ArmDataProcImm() {{
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pclr = '''
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return new %(className)ssImmPclr(machInst, %(dest)s,
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%(op1)s, imm, false);
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'''
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adr = '''
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return new AdrImm(machInst, %(dest)s, %(add)s,
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imm, false);
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'''
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instDecode = '''
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case %(opcode)#x:
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if (setCc) {
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return new %(className)sImmCc(machInst, %(dest)s, %(op1)s,
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imm, rotC);
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if (%(pclrInst)s && %(dest)s == INTREG_PC) {
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%(pclr)s
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} else {
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return new %(className)sImmCc(machInst, %(dest)s, %(op1)s,
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imm, rotC);
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}
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} else {
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return new %(className)sImm(machInst, %(dest)s, %(op1)s,
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imm, rotC);
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if (%(adrInst)s && %(op1)s == INTREG_PC) {
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%(adr)s
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} else {
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return new %(className)sImm(machInst, %(dest)s, %(op1)s,
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imm, rotC);
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}
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}
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break;
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'''
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def instCode(opcode, mnem, dest="rd", op1="rn"):
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global instDecode
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code = '''
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case %(opcode)#x:
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''' + instDecode
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return code % { "className": mnem.capitalize(),
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"opcode": opcode,
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"dest": dest,
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"op1": op1 }
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def instCode(opcode, mnem, useDest = True, useOp1 = True):
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global instDecode, pclr, adr
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if useDest:
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dest = "rd"
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else:
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dest = "INTREG_ZERO"
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if useOp1:
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op1 = "rn"
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else:
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op1 = "INTREG_ZERO"
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substDict = { "className": mnem.capitalize(),
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"opcode": opcode,
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"dest": dest,
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"op1": op1,
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"adr": "",
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"adrInst": "false" }
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if useDest:
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substDict["pclrInst"] = "true"
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substDict["pclr"] = pclr % substDict
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else:
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substDict["pclrInst"] = "false"
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substDict["pclr"] = ""
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return instDecode % substDict
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def adrCode(opcode, mnem, dest="rd", op1="rn", add="1"):
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global instDecode
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code = '''
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case %(opcode)#x:
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if (rn == 0xf) {
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return new AdrImm(machInst, %(dest)s, %(add)s,
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imm, false);
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} else {
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''' + instDecode + '''
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}
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'''
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return code % { "className": mnem.capitalize(),
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"opcode": opcode,
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"dest": dest,
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"add": add,
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"op1": op1 }
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def adrCode(opcode, mnem, add="1"):
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global instDecode, pclr, adr
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substDict = { "className": mnem.capitalize(),
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"opcode": opcode,
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"dest": "rd",
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"op1": "rn",
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"add": add,
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"pclrInst": "true",
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"adrInst": "true" }
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substDict["pclr"] = pclr % substDict
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substDict["adr"] = adr % substDict
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return instDecode % substDict
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decode_block = '''
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{
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@ -159,14 +209,14 @@ def format ArmDataProcImm() {{
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decode_block += instCode(0x5, "adc")
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decode_block += instCode(0x6, "sbc")
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decode_block += instCode(0x7, "rsc")
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decode_block += instCode(0x8, "tst", dest="INTREG_ZERO")
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decode_block += instCode(0x9, "teq", dest="INTREG_ZERO")
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decode_block += instCode(0xa, "cmp", dest="INTREG_ZERO")
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decode_block += instCode(0xb, "cmn", dest="INTREG_ZERO")
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decode_block += instCode(0x8, "tst", useDest = False)
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decode_block += instCode(0x9, "teq", useDest = False)
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decode_block += instCode(0xa, "cmp", useDest = False)
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decode_block += instCode(0xb, "cmn", useDest = False)
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decode_block += instCode(0xc, "orr")
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decode_block += instCode(0xd, "mov", op1="INTREG_ZERO")
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decode_block += instCode(0xd, "mov", useOp1 = False)
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decode_block += instCode(0xe, "bic")
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decode_block += instCode(0xf, "mvn", op1="INTREG_ZERO")
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decode_block += instCode(0xf, "mvn", useOp1 = False)
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decode_block += '''
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default:
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return new Unknown(machInst);
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@ -98,8 +98,8 @@ let {{
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regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
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regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
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def buildImmDataInst(mnem, code, flagType = "logic"):
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global header_output, decoder_output, exec_output
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def buildImmDataInst(mnem, code, flagType = "logic", \
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suffix = "Imm", buildCc = True):
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cCode = carryCode[flagType]
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vCode = overflowCode[flagType]
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negBit = 31
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@ -114,22 +114,26 @@ let {{
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"negBit": negBit
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}
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immCode = secondOpRe.sub(immOp2, code)
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immIop = InstObjParams(mnem, mnem.capitalize() + "Imm", "DataImmOp",
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immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
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{"code" : immCode,
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"predicate_test": predicateTest})
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immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "ImmCc",
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immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
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"DataImmOp",
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{"code" : immCode + immCcCode,
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"predicate_test": predicateTest})
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header_output += DataImmDeclare.subst(immIop) + \
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DataImmDeclare.subst(immIopCc)
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decoder_output += DataImmConstructor.subst(immIop) + \
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DataImmConstructor.subst(immIopCc)
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exec_output += PredOpExecute.subst(immIop) + \
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PredOpExecute.subst(immIopCc)
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def buildRegDataInst(mnem, code, flagType = "logic"):
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global header_output, decoder_output, exec_output
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def subst(iop):
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global header_output, decoder_output, exec_output
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header_output += DataImmDeclare.subst(iop)
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decoder_output += DataImmConstructor.subst(iop)
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exec_output += PredOpExecute.subst(iop)
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subst(immIop)
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if buildCc:
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subst(immIopCc)
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def buildRegDataInst(mnem, code, flagType = "logic", \
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suffix = "Reg", buildCc = True):
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cCode = carryCode[flagType]
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vCode = overflowCode[flagType]
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negBit = 31
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@ -144,22 +148,26 @@ let {{
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"negBit": negBit
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}
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regCode = secondOpRe.sub(regOp2, code)
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regIop = InstObjParams(mnem, mnem.capitalize() + "Reg", "DataRegOp",
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regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
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{"code" : regCode,
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"predicate_test": predicateTest})
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regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "RegCc",
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regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
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"DataRegOp",
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{"code" : regCode + regCcCode,
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"predicate_test": predicateTest})
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header_output += DataRegDeclare.subst(regIop) + \
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DataRegDeclare.subst(regIopCc)
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decoder_output += DataRegConstructor.subst(regIop) + \
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DataRegConstructor.subst(regIopCc)
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exec_output += PredOpExecute.subst(regIop) + \
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PredOpExecute.subst(regIopCc)
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def buildRegRegDataInst(mnem, code, flagType = "logic"):
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global header_output, decoder_output, exec_output
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def subst(iop):
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global header_output, decoder_output, exec_output
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header_output += DataRegDeclare.subst(iop)
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decoder_output += DataRegConstructor.subst(iop)
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exec_output += PredOpExecute.subst(iop)
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subst(regIop)
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if buildCc:
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subst(regIopCc)
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def buildRegRegDataInst(mnem, code, flagType = "logic", \
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suffix = "RegReg", buildCc = True):
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cCode = carryCode[flagType]
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vCode = overflowCode[flagType]
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negBit = 31
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@ -174,53 +182,72 @@ let {{
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"negBit": negBit
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}
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regRegCode = secondOpRe.sub(regRegOp2, code)
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regRegIop = InstObjParams(mnem, mnem.capitalize() + "RegReg",
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regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix,
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"DataRegRegOp",
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{"code" : regRegCode,
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"predicate_test": predicateTest})
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regRegIopCc = InstObjParams(mnem + "s",
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mnem.capitalize() + "RegRegCc",
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mnem.capitalize() + suffix + "Cc",
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"DataRegRegOp",
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{"code" : regRegCode + regRegCcCode,
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"predicate_test": predicateTest})
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header_output += DataRegRegDeclare.subst(regRegIop) + \
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DataRegRegDeclare.subst(regRegIopCc)
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decoder_output += DataRegRegConstructor.subst(regRegIop) + \
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DataRegRegConstructor.subst(regRegIopCc)
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exec_output += PredOpExecute.subst(regRegIop) + \
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PredOpExecute.subst(regRegIopCc)
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def buildDataInst(mnem, code, flagType = "logic"):
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buildImmDataInst(mnem, code, flagType)
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buildRegDataInst(mnem, code, flagType)
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buildRegRegDataInst(mnem, code, flagType)
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def subst(iop):
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global header_output, decoder_output, exec_output
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header_output += DataRegRegDeclare.subst(iop)
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decoder_output += DataRegRegConstructor.subst(iop)
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exec_output += PredOpExecute.subst(iop)
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buildDataInst("and", "AIWDest = resTemp = Op1 & secondOp;")
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buildDataInst("eor", "AIWDest = resTemp = Op1 ^ secondOp;")
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buildDataInst("sub", "AIWDest = resTemp = Op1 - secondOp;", "sub")
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buildDataInst("rsb", "AIWDest = resTemp = secondOp - Op1;", "rsb")
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buildDataInst("add", "AIWDest = resTemp = Op1 + secondOp;", "add")
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subst(regRegIop)
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if buildCc:
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subst(regRegIopCc)
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def buildDataInst(mnem, code, flagType = "logic", \
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aiw = True, regRegAiw = True,
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subsPcLr = True):
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regRegCode = instCode = code
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if aiw:
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instCode = "AIW" + instCode
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if regRegAiw:
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regRegCode = "AIW" + regRegCode
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buildImmDataInst(mnem, instCode, flagType)
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buildRegDataInst(mnem, instCode, flagType)
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buildRegRegDataInst(mnem, regRegCode, flagType)
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if subsPcLr:
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code += '''
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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'''
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buildImmDataInst(mnem + 's', code, flagType,
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suffix = "ImmPclr", buildCc = False)
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buildRegDataInst(mnem + 's', code, flagType,
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suffix = "RegPclr", buildCc = False)
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buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
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buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")
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buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub")
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buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
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buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add")
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buildImmDataInst("adr", '''
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AIWDest = resTemp = (readPC(xc) & ~0x3) +
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Dest = resTemp = (readPC(xc) & ~0x3) +
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(op1 ? secondOp : -secondOp);
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''')
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buildDataInst("adc", "AIWDest = resTemp = Op1 + secondOp + %s;" % oldC,
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"add")
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buildDataInst("sbc", "AIWDest = resTemp = Op1 - secondOp - !%s;" % oldC,
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"sub")
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buildDataInst("rsc", "AIWDest = resTemp = secondOp - Op1 - !%s;" % oldC,
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"rsb")
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buildDataInst("tst", "resTemp = Op1 & secondOp;")
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buildDataInst("teq", "resTemp = Op1 ^ secondOp;")
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buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub")
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buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add")
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buildDataInst("orr", "AIWDest = resTemp = Op1 | secondOp;")
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buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;")
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buildImmDataInst("mov", "AIWDest = resTemp = secondOp;")
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buildRegDataInst("mov", "AIWDest = resTemp = secondOp;")
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buildRegRegDataInst("mov", "Dest = resTemp = secondOp;")
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buildDataInst("bic", "AIWDest = resTemp = Op1 & ~secondOp;")
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buildDataInst("mvn", "AIWDest = resTemp = ~secondOp;")
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buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")
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buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub")
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buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb")
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buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False)
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buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False)
|
||||
buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False)
|
||||
buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False)
|
||||
buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
|
||||
buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
|
||||
buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False)
|
||||
buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
|
||||
buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
|
||||
buildDataInst("movt",
|
||||
"Dest = resTemp = insertBits(Op1, 31, 16, secondOp);")
|
||||
"Dest = resTemp = insertBits(Op1, 31, 16, secondOp);",
|
||||
aiw = False)
|
||||
}};
|
||||
|
|
|
|||
Loading…
Reference in a new issue