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ARM: Centralize the declaration of resTemp.

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This commit is contained in:
Gabe Black 2009-07-01 22:15:39 -07:00
parent 776a06fd39
commit ce9cb1ecb5
2 changed files with 36 additions and 61 deletions
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94
src/arch/arm/isa/decoder.isa
View file

@ -83,30 +83,25 @@ format DataOp {
1: decode MISC_OPCODE {
0x9: decode PREPOST {
0: decode OPCODE {
0x0: mul({{ uint32_t resTemp;
Rn = resTemp = Rm * Rs; }},
0x0: mul({{ Rn = resTemp = Rm * Rs; }},
{{ Cpsr<29:> }},
{{ Cpsr<28:> }});
0x1: mla({{ uint32_t resTemp;
Rn = resTemp = Rm * Rs; }},
0x1: mla({{ Rn = resTemp = Rm * Rs; }},
{{ Cpsr<29:> }},
{{ Cpsr<28:> }});
0x2: WarnUnimpl::umall();
0x4: umull({{
uint64_t resTemp;
resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
Rd = (uint32_t)(resTemp & 0xffffffff);
Rn = (uint32_t)(resTemp >> 32);
}}, {{ 1 }}, {{ 1 }});
0x5: WarnUnimpl::smlal();
0x6: smull({{
int64_t resTemp;
resTemp = ((int64_t)Rm.sw)*((int64_t)Rs.sw);
Rd = (int32_t)(resTemp & 0xffffffff);
Rn = (int32_t)(resTemp >> 32);
}}, {{ 1 }}, {{ 1 }});
0x7: umlal({{
uint64_t resTemp;
resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
Rd = (uint32_t)(resTemp & 0xffffffff);
@ -231,66 +226,61 @@ format DataOp {
}
0: decode IS_MISC {
0: decode OPCODE {
0x0: and({{ uint32_t resTemp;
Rd = resTemp = Rn & op2; }},
0x0: and({{ Rd = resTemp = Rn & op2; }},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
0x1: eor({{ uint32_t resTemp;
Rd = resTemp = Rn ^ op2; }},
0x1: eor({{ Rd = resTemp = Rn ^ op2; }},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
0x2: sub({{ uint32_t resTemp, val2 = op2;
0x2: sub({{ uint32_t val2 = op2;
Rd = resTemp = Rn - val2; }},
{{ arm_sub_carry(resTemp, Rn, val2) }},
{{ arm_sub_overflow(resTemp, Rn, val2) }});
0x3: rsb({{ uint32_t resTemp, val2 = op2;
0x3: rsb({{ uint32_t val2 = op2;
Rd = resTemp = val2 - Rn; }},
{{ arm_sub_carry(resTemp, val2, Rn) }},
{{ arm_sub_overflow(resTemp, val2, Rn) }});
0x4: add({{ uint32_t resTemp, val2 = op2;
0x4: add({{ uint32_t val2 = op2;
Rd = resTemp = Rn + val2; }},
{{ arm_add_carry(resTemp, Rn, val2) }},
{{ arm_add_overflow(resTemp, Rn, val2) }});
0x5: adc({{ uint32_t resTemp, val2 = op2;
0x5: adc({{ uint32_t val2 = op2;
Rd = resTemp = Rn + val2 + Cpsr<29:>; }},
{{ arm_add_carry(resTemp, Rn, val2) }},
{{ arm_add_overflow(resTemp, Rn, val2) }});
0x6: sbc({{ uint32_t resTemp, val2 = op2;
0x6: sbc({{ uint32_t val2 = op2;
Rd = resTemp = Rn - val2 - !Cpsr<29:>; }},
{{ arm_sub_carry(resTemp, Rn, val2) }},
{{ arm_sub_overflow(resTemp, Rn, val2) }});
0x7: rsc({{ uint32_t resTemp, val2 = op2;
0x7: rsc({{ uint32_t val2 = op2;
Rd = resTemp = val2 - Rn - !Cpsr<29:>; }},
{{ arm_sub_carry(resTemp, val2, Rn) }},
{{ arm_sub_overflow(resTemp, val2, Rn) }});
0x8: tst({{ uint32_t resTemp = Rn & op2; }},
0x8: tst({{ resTemp = Rn & op2; }},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
0x9: teq({{ uint32_t resTemp = Rn ^ op2; }},
0x9: teq({{ resTemp = Rn ^ op2; }},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
0xa: cmp({{ uint32_t resTemp, val2 = op2;
0xa: cmp({{ uint32_t val2 = op2;
resTemp = Rn - val2; }},
{{ arm_sub_carry(resTemp, Rn, val2) }},
{{ arm_sub_overflow(resTemp, Rn, val2) }});
0xb: cmn({{ uint32_t resTemp, val2 = op2;
0xb: cmn({{ uint32_t val2 = op2;
resTemp = Rn + val2; }},
{{ arm_add_carry(resTemp, Rn, val2) }},
{{ arm_add_overflow(resTemp, Rn, val2) }});
0xc: orr({{ uint32_t resTemp, val2 = op2;
0xc: orr({{ uint32_t val2 = op2;
Rd = resTemp = Rn | val2; }},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
0xd: mov({{ uint32_t resTemp;
Rd = resTemp = op2; }},
0xd: mov({{ Rd = resTemp = op2; }},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
0xe: bic({{ uint32_t resTemp;
Rd = resTemp = Rn & ~op2; }},
0xe: bic({{ Rd = resTemp = Rn & ~op2; }},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
0xf: mvn({{ uint32_t resTemp;
Rd = resTemp = ~op2; }},
0xf: mvn({{ Rd = resTemp = ~op2; }},
{{ shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>) }},
{{ Cpsr<28:> }});
}
@ -360,68 +350,52 @@ format DataOp {
0x1: decode IS_MISC {
0: decode OPCODE {
format DataImmOp {
0x0: andi({{ uint32_t resTemp;
Rd = resTemp = Rn & rotated_imm; }},
0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }},
{{ (rotate ? rotated_carry:Cpsr<29:>) }},
{{ Cpsr<28:> }});
0x1: eori({{ uint32_t resTemp;
Rd = resTemp = Rn ^ rotated_imm; }},
0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }},
{{ (rotate ? rotated_carry:Cpsr<29:>) }},
{{ Cpsr<28:> }});
0x2: subi({{ uint32_t resTemp;
Rd = resTemp = Rn - rotated_imm; }},
0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }},
{{ arm_sub_carry(resTemp, Rn, rotated_imm) }},
{{ arm_sub_overflow(resTemp, Rn, rotated_imm) }});
0x3: rsbi({{ uint32_t resTemp;
Rd = resTemp = rotated_imm - Rn; }},
0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }},
{{ arm_sub_carry(resTemp, rotated_imm, Rn) }},
{{ arm_sub_overflow(resTemp, rotated_imm, Rn) }});
0x4: addi({{ uint32_t resTemp;
Rd = resTemp = Rn + rotated_imm; }},
0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }},
{{ arm_add_carry(resTemp, Rn, rotated_imm) }},
{{ arm_add_overflow(resTemp, Rn, rotated_imm) }});
0x5: adci({{ uint32_t resTemp;
Rd = resTemp = Rn + rotated_imm + Cpsr<29:>; }},
0x5: adci({{ Rd = resTemp = Rn + rotated_imm + Cpsr<29:>; }},
{{ arm_add_carry(resTemp, Rn, rotated_imm) }},
{{ arm_add_overflow(resTemp, Rn, rotated_imm) }});
0x6: sbci({{ uint32_t resTemp;
Rd = resTemp = Rn -rotated_imm - !Cpsr<29:>; }},
0x6: sbci({{ Rd = resTemp = Rn -rotated_imm - !Cpsr<29:>; }},
{{ arm_sub_carry(resTemp, Rn, rotated_imm) }},
{{ arm_sub_overflow(resTemp, Rn, rotated_imm) }});
0x7: rsci({{ uint32_t resTemp;
Rd = resTemp = rotated_imm - Rn - !Cpsr<29:>;}},
0x7: rsci({{ Rd = resTemp = rotated_imm - Rn - !Cpsr<29:>;}},
{{ arm_sub_carry(resTemp, rotated_imm, Rn) }},
{{ arm_sub_overflow(resTemp, rotated_imm, Rn) }});
0x8: tsti({{ uint32_t resTemp;
resTemp = Rn & rotated_imm; }},
0x8: tsti({{ resTemp = Rn & rotated_imm; }},
{{ (rotate ? rotated_carry:Cpsr<29:>) }},
{{ Cpsr<28:> }});
0x9: teqi({{ uint32_t resTemp;
resTemp = Rn ^ rotated_imm; }},
0x9: teqi({{ resTemp = Rn ^ rotated_imm; }},
{{ (rotate ? rotated_carry:Cpsr<29:>) }},
{{ Cpsr<28:> }});
0xa: cmpi({{ uint32_t resTemp;
resTemp = Rn - rotated_imm; }},
0xa: cmpi({{ resTemp = Rn - rotated_imm; }},
{{ arm_sub_carry(resTemp, Rn, rotated_imm) }},
{{ arm_sub_overflow(resTemp, Rn, rotated_imm) }});
0xb: cmni({{ uint32_t resTemp;
resTemp = Rn + rotated_imm; }},
0xb: cmni({{ resTemp = Rn + rotated_imm; }},
{{ arm_add_carry(resTemp, Rn, rotated_imm) }},
{{ arm_add_overflow(resTemp, Rn, rotated_imm) }});
0xc: orri({{ uint32_t resTemp;
Rd = resTemp = Rn | rotated_imm; }},
0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }},
{{ (rotate ? rotated_carry:Cpsr<29:>) }},
{{ Cpsr<28:> }});
0xd: movi({{ uint32_t resTemp;
Rd = resTemp = rotated_imm; }},
0xd: movi({{ Rd = resTemp = rotated_imm; }},
{{ (rotate ? rotated_carry:Cpsr<29:>) }},
{{ Cpsr<28:> }});
0xe: bici({{ uint32_t resTemp;
Rd = resTemp = Rn & ~rotated_imm; }},
0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }},
{{ (rotate ? rotated_carry:Cpsr<29:>) }},
{{ Cpsr<28:> }});
0xf: mvni({{ uint32_t resTemp;
Rd = resTemp = ~rotated_imm; }},
0xf: mvni({{ Rd = resTemp = ~rotated_imm; }},
{{ (rotate ? rotated_carry:Cpsr<29:>) }},
{{ Cpsr<28:> }});
}

3
src/arch/arm/isa/formats/pred.isa
View file

@ -41,6 +41,8 @@ def template PredOpExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t resTemp = 0;
resTemp = resTemp;
%(op_decl)s;
%(op_rd)s;
@ -100,7 +102,6 @@ let {{
}};
def format DataOp(code, icValue, ivValue) {{
code += "resTemp = resTemp;"
regCode = re.sub(r'op2', 'shift_rm_rs(Rm, Rs, \
shift, Cpsr<29:0>)', code)
immCode = re.sub(r'op2', 'shift_rm_imm(Rm, shift_size, \