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SPARC: Adjust a few instructions to not write registers in initiateAcc.

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This commit is contained in:
Gabe Black 2009-02-25 10:16:04 -08:00
parent 1b336a8fe7
commit 15940d06b5
3 changed files with 27 additions and 15 deletions
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18
src/arch/sparc/isa/decoder.isa
View file

@ -1231,16 +1231,14 @@ decode OP default Unknown::unknown()
0x23: Load::lddf({{Frd.udw = Mem.udw;}});
0x24: Store::stf({{Mem.uw = Frds.uw;}});
0x25: decode RD {
0x0: Store::stfsr({{fault = checkFpEnableFault(xc);
if (fault)
return fault;
Mem.uw = Fsr<31:0>;
Fsr = insertBits(Fsr,16,14,0);}});
0x1: Store::stxfsr({{fault = checkFpEnableFault(xc);
if (fault)
return fault;
Mem.udw = Fsr;
Fsr = insertBits(Fsr,16,14,0);}});
0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc);
if (fault)
return fault;
Mem.uw = Fsr<31:0>;}});
0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc);
if (fault)
return fault;
Mem.udw = Fsr;}});
default: FailUnimpl::stfsrOther();
}
0x26: stqf({{fault = new FpDisabled;}});

10
src/arch/sparc/isa/formats/mem/basicmem.isa
View file

@ -108,6 +108,16 @@ def format Store(code, *opt_flags) {{
StoreFuncs, '', name, Name, 0, opt_flags)
}};
def format StoreFsr(code, *opt_flags) {{
code = filterDoubles(code)
(header_output,
decoder_output,
exec_output,
decode_block) = doMemFormat(code,
StoreFuncs, '', name, Name, 0, opt_flags,
'Fsr = insertBits(Fsr,16,14,0);')
}};
def format TwinLoad(code, *opt_flags) {{
(header_output,
decoder_output,

14
src/arch/sparc/isa/formats/mem/util.isa
View file

@ -264,11 +264,6 @@ def template StoreInitiateAcc {{
fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, 0);
}
if(fault == NoFault)
{
//Write the resulting state to the execution context
%(op_wb)s;
}
return fault;
}
}};
@ -277,6 +272,15 @@ def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
Trace::InstRecord * traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
%(postacc_code)s;
if (fault == NoFault)
{
%(op_wb)s;
}
return NoFault;
}
}};