Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something.

--HG--
extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89
This commit is contained in:
Ali Saidi 2007-12-18 01:52:57 -05:00
parent 71909a50de
commit 45ea1549c9
2 changed files with 3 additions and 3 deletions

View file

@ -91,7 +91,7 @@ def run(options, root, testsys, cpu_class):
switch_cpus[i].workload = testsys.cpu[i].workload
switch_cpus[i].clock = testsys.cpu[0].clock
root.switch_cpus = switch_cpus
testsys.switch_cpus = switch_cpus
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
if options.standard_switch:

View file

@ -352,7 +352,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
// connected to anything. Also connect old CPU's memory to new
// CPU.
Port *peer;
if (ic->getPeer() == NULL) {
if (ic->getPeer() == NULL || ic->getPeer()->isDefaultPort()) {
peer = oldCPU->getPort("icache_port")->getPeer();
ic->setPeer(peer);
} else {
@ -360,7 +360,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
}
peer->setPeer(ic);
if (dc->getPeer() == NULL) {
if (dc->getPeer() == NULL || dc->getPeer()->isDefaultPort()) {
peer = oldCPU->getPort("dcache_port")->getPeer();
dc->setPeer(peer);
} else {