sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

X86: Make instructions that use intseg preserve all 8 bytes of their addresses.

Browse source
This commit is contained in:
Gabe Black 2009-02-27 09:25:02 -08:00
parent 79bc1b3740
commit 1d18eb9043
2 changed files with 6 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
View file

@ -85,22 +85,22 @@ microcode = '''
def macroop IN_R_I {
.adjust_imm trimImm(8)
limm t1, imm, dataSize=asz
ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8
};
def macroop IN_R_R {
zexti t2, regm, 15, dataSize=8
ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
};
def macroop OUT_I_R {
.adjust_imm trimImm(8)
limm t1, imm, dataSize=8
st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8
};
def macroop OUT_R_R {
zexti t2, reg, 15, dataSize=8
st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
};
'''

4
src/arch/x86/isa/insts/system/msrs.py
View file

@ -85,7 +85,7 @@ microcode = '''
def macroop RDMSR
{
ld t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
dataSize=8, addressSize=4
dataSize=8, addressSize=8
mov rax, rax, t2, dataSize=4
srli t2, t2, 32, dataSize=8
mov rdx, rdx, t2, dataSize=4
@ -97,7 +97,7 @@ def macroop WRMSR
slli t3, rdx, 32, dataSize=8
or t2, t2, t3, dataSize=8
st t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
dataSize=8, addressSize=4
dataSize=8, addressSize=8
};
def macroop RDTSC