ARM: Implement data processing instructions external to the decoder.
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Gabe Black
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c02f9cdddf
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188
src/arch/arm/isa/insts/data.isa
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188
src/arch/arm/isa/insts/data.isa
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// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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let {{
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header_output = ""
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decoder_output = ""
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exec_output = ""
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calcQCode = '''
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cprintf("canOverflow: %%d\\n", Dest < resTemp);
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replaceBits(CondCodes, 27, Dest < resTemp);
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'''
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calcCcCode = '''
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uint16_t _ic, _iv, _iz, _in;
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_in = (resTemp >> %(negBit)d) & 1;
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_iz = (resTemp == 0);
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_iv = %(ivValue)s & 1;
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_ic = %(icValue)s & 1;
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CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
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(CondCodes & 0x0FFFFFFF);
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DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n",
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_in, _iz, _ic, _iv);
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'''
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# Dict of code to set the carry flag. (imm, reg, reg-reg)
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oldC = 'CondCodes<29:>'
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oldV = 'CondCodes<28:>'
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carryCode = {
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"none": (oldC, oldC, oldC),
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"llbit": (oldC, oldC, oldC),
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"overflow": ('0', '0', '0'),
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"add": ('findCarry(32, resTemp, Op1, secondOp)',
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'findCarry(32, resTemp, Op1, secondOp)',
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'findCarry(32, resTemp, Op1, secondOp)'),
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"sub": ('findCarry(32, resTemp, Op1, ~secondOp)',
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'findCarry(32, resTemp, Op1, ~secondOp)',
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'findCarry(32, resTemp, Op1, ~secondOp)'),
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"rsb": ('findCarry(32, resTemp, secondOp, ~Op1)',
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'findCarry(32, resTemp, secondOp, ~Op1)',
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'findCarry(32, resTemp, secondOp, ~Op1)'),
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"logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC,
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'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC,
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'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC)
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}
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# Dict of code to set the overflow flag.
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overflowCode = {
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"none": oldV,
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"llbit": oldV,
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"overflow": '0',
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"add": 'findOverflow(32, resTemp, Op1, secondOp)',
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"sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
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"rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
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"logic": oldV
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}
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secondOpRe = re.compile("secondOp")
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immOp2 = "imm"
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regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
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regRegOp2 = "shift_rm_rs(Op2, Shift, shiftType, CondCodes<29:>)"
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def buildDataInst(mnem, code, flagType = "logic"):
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global header_output, decoder_output, exec_output
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cCode = carryCode[flagType]
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vCode = overflowCode[flagType]
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negBit = 31
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if flagType == "llbit":
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negBit = 63
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if flagType == "overflow":
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immCcCode = regCcCode = regRegCcCode = calcQCode
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else:
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immCcCode = calcCcCode % {
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"icValue": secondOpRe.sub(immOp2, cCode[0]),
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"ivValue": secondOpRe.sub(immOp2, vCode),
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"negBit": negBit
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}
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regCcCode = calcCcCode % {
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"icValue": secondOpRe.sub(regOp2, cCode[1]),
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"ivValue": secondOpRe.sub(regOp2, vCode),
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"negBit": negBit
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}
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regRegCcCode = calcCcCode % {
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"icValue": secondOpRe.sub(regRegOp2, cCode[2]),
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"ivValue": secondOpRe.sub(regRegOp2, vCode),
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"negBit": negBit
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}
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immCode = secondOpRe.sub(immOp2, code)
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regCode = secondOpRe.sub(regOp2, code)
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regRegCode = secondOpRe.sub(regRegOp2, code)
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immIop = InstObjParams(mnem, mnem.capitalize() + "DImm", "DataImmOp",
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{"code" : immCode,
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"predicate_test": predicateTest})
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regIop = InstObjParams(mnem, mnem.capitalize() + "DReg", "DataRegOp",
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{"code" : regCode,
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"predicate_test": predicateTest})
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regRegIop = InstObjParams(mnem, mnem.capitalize() + "DRegReg",
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"DataRegRegOp",
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{"code" : regRegCode,
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"predicate_test": predicateTest})
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immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "DImmCc",
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"DataImmOp",
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{"code" : immCode + immCcCode,
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"predicate_test": predicateTest})
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regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + "DRegCc",
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"DataRegOp",
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{"code" : regCode + regCcCode,
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"predicate_test": predicateTest})
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regRegIopCc = InstObjParams(mnem + "s",
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mnem.capitalize() + "DRegRegCc",
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"DataRegRegOp",
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{"code" : regRegCode + regRegCcCode,
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"predicate_test": predicateTest})
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header_output += DataImmDeclare.subst(immIop) + \
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DataImmDeclare.subst(immIopCc) + \
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DataRegDeclare.subst(regIop) + \
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DataRegDeclare.subst(regIopCc) + \
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DataRegRegDeclare.subst(regRegIop) + \
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DataRegRegDeclare.subst(regRegIopCc)
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decoder_output += DataImmConstructor.subst(immIop) + \
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DataImmConstructor.subst(immIopCc) + \
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DataRegConstructor.subst(regIop) + \
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DataRegConstructor.subst(regIopCc) + \
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DataRegRegConstructor.subst(regRegIop) + \
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DataRegRegConstructor.subst(regRegIopCc)
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exec_output += PredOpExecute.subst(immIop) + \
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PredOpExecute.subst(immIopCc) + \
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PredOpExecute.subst(regIop) + \
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PredOpExecute.subst(regIopCc) + \
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PredOpExecute.subst(regRegIop) + \
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PredOpExecute.subst(regRegIopCc)
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buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
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buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")
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buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub")
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buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
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buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add")
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buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")
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buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub")
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buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb")
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buildDataInst("tst", "resTemp = Op1 & secondOp;")
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buildDataInst("teq", "resTemp = Op1 ^ secondOp;")
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buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub")
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buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add")
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buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
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buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;")
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buildDataInst("mov", "Dest = resTemp = secondOp;")
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buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
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buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
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}};
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@ -51,3 +51,6 @@
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//Load/store multiple
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##include "macromem.isa"
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//Data processing instructions
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##include "data.isa"
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@ -49,6 +49,82 @@ let {{
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predicateTest = 'testPredicate(CondCodes, condCode)'
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}};
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def template DataImmDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
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IntRegIndex _op1, uint32_t _imm, bool _rotC=true);
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%(BasicExecDeclare)s
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};
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}};
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def template DataImmConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest,
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IntRegIndex _op1,
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uint32_t _imm,
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bool _rotC)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _imm, _rotC)
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{
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%(constructor)s;
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}
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}};
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def template DataRegDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
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IntRegIndex _op1, IntRegIndex _op2,
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int32_t _shiftAmt, ArmShiftType _shiftType);
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%(BasicExecDeclare)s
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};
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}};
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def template DataRegConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest,
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IntRegIndex _op1,
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IntRegIndex _op2,
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int32_t _shiftAmt,
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ArmShiftType _shiftType)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _op2, _shiftAmt, _shiftType)
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{
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%(constructor)s;
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}
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}};
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def template DataRegRegDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
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IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift,
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ArmShiftType _shiftType);
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%(BasicExecDeclare)s
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};
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}};
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def template DataRegRegConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest,
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IntRegIndex _op1,
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IntRegIndex _op2,
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IntRegIndex _shift,
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ArmShiftType _shiftType)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _op2, _shift, _shiftType)
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{
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%(constructor)s;
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}
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}};
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def template PredOpExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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