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CPU: Don't fetch when executing a macroop.

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If the CPL changes mid macroop, the end of the instruction might not be
priveleged enough to execute the beginning.
This commit is contained in:
Gabe Black 2009-02-25 10:18:36 -08:00
parent ba69184630
commit da61c4b3ee
2 changed files with 3 additions and 3 deletions
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4
src/cpu/simple/atomic.cc
View file

@ -607,7 +607,7 @@ AtomicSimpleCPU::tick()
Fault fault = NoFault;
bool fromRom = isRomMicroPC(thread->readMicroPC());
if (!fromRom) {
if (!fromRom && !curMacroStaticInst) {
setupFetchRequest(&ifetch_req);
fault = thread->itb->translateAtomic(&ifetch_req, tc);
}
@ -617,7 +617,7 @@ AtomicSimpleCPU::tick()
bool icache_access = false;
dcache_access = false; // assume no dcache access
if (!fromRom) {
if (!fromRom && !curMacroStaticInst) {
// This is commented out because the predecoder would act like
// a tiny cache otherwise. It wouldn't be flushed when needed
// like the I cache. It should be flushed, and when that works

2
src/cpu/simple/timing.cc
View file

@ -667,7 +667,7 @@ TimingSimpleCPU::fetch()
bool fromRom = isRomMicroPC(thread->readMicroPC());
if (!fromRom) {
if (!fromRom && !curMacroStaticInst) {
Request *ifetch_req = new Request();
ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
setupFetchRequest(ifetch_req);