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X86: Fix the ordering of special physical address ranges.

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This commit is contained in:
Gabe Black 2008-10-12 14:01:06 -07:00
parent 3a1905157e
commit d0a43ce2b2
2 changed files with 3 additions and 3 deletions
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4
src/arch/x86/x86_traits.hh
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@ -92,8 +92,8 @@ namespace X86ISA
const Addr PhysAddrPrefixIO = ULL(0x8000000000000000);
const Addr PhysAddrPrefixPciConfig = ULL(0xC000000000000000);
const Addr PhysAddrPrefixLocalAPIC = ULL(0xA000000000000000);
const Addr PhysAddrPrefixInterrupts = ULL(0x2000000000000000);
const Addr PhysAddrPrefixLocalAPIC = ULL(0x2000000000000000);
const Addr PhysAddrPrefixInterrupts = ULL(0xA000000000000000);
// Each APIC gets two pages. One page is used for local apics to field
// accesses from the CPU, and the other is for all APICs to communicate.
const Addr PhysAddrAPICRangeSize = 1 << 12;

2
src/cpu/BaseCPU.py
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@ -97,7 +97,7 @@ class BaseCPU(MemObject):
dtb = Param.X86DTB(X86DTB(), "Data TLB")
itb = Param.X86ITB(X86ITB(), "Instruction TLB")
if build_env['FULL_SYSTEM']:
_localApic = X86LocalApic(pio_addr=0xa000000000000000)
_localApic = X86LocalApic(pio_addr=0x2000000000000000)
interrupts = \
Param.X86LocalApic(_localApic, "Interrupt Controller")
elif build_env['TARGET_ISA'] == 'mips':