Config adjustments for MESI
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Polina Dudnik
parent
fc9ebc60db
commit
8cdd7265ce
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@ -26,7 +26,7 @@ num_memories = 1
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memory_size_mb = 1024
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num_dma = 1
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protocol = "MOESI_CMP_directory"
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protocol = "MESI_CMP_directory"
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# check for overrides
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@ -49,7 +49,7 @@ end
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net_ports = Array.new
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iface_ports = Array.new
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assert(protocol == "MOESI_CMP_directory", __FILE__+" cannot be used with protocol "+protocol);
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#assert(protocol == "MESI_CMP_directory", __FILE__+" cannot be used with protocol "+protocol);
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require protocol+".rb"
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@ -65,6 +65,14 @@ num_cores.times { |n|
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sequencer,
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num_l2_banks)
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end
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if protocol == "MESI_CMP_directory"
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net_ports << MESI_CMP_directory_L1CacheController.new("L1CacheController_"+n.to_s,
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"L1Cache",
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icache, dcache,
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sequencer,
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num_l2_banks)
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end
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}
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num_l2_banks.times { |n|
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cache = SetAssociativeCache.new("l2u_"+n.to_s, l2_cache_size_kb/num_l2_banks, l2_cache_latency, l2_cache_assoc, "PSEUDO_LRU")
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@ -73,6 +81,14 @@ num_l2_banks.times { |n|
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"L2Cache",
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cache)
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end
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if protocol == "MESI_CMP_directory"
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net_ports << MESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s,
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"L2Cache",
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cache)
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end
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}
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num_memories.times { |n|
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directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s, memory_size_mb/num_memories)
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@ -83,6 +99,14 @@ num_memories.times { |n|
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directory,
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memory_control)
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end
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if protocol == "MESI_CMP_directory"
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net_ports << MESI_CMP_directory_DirectoryController.new("DirectoryController_"+n.to_s,
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"Directory",
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directory,
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memory_control)
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end
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}
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num_dma.times { |n|
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dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s)
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@ -92,6 +116,14 @@ num_dma.times { |n|
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"DMA",
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dma_sequencer)
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end
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if protocol == "MESI_CMP_directory"
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net_ports << MESI_CMP_directory_DMAController.new("DMAController_"+n.to_s,
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"DMA",
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dma_sequencer)
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end
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}
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topology = CrossbarTopology.new("theTopology", net_ports)
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@ -296,7 +296,6 @@ private
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end
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#require "defaults.rb"
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@ -439,27 +438,27 @@ class SetAssociativeCache < Cache
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cacti_args << 360 << 0 << 0 << 0 << 0 << 1 << 1 << 1 << 1 << 0 << 0
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cacti_args << 50 << 10 << 10 << 0 << 1 << 1
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cacti_cmd = File.dirname(__FILE__) + "/cacti/cacti " + cacti_args.join(" ")
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# cacti_cmd = File.dirname(__FILE__) + "/cacti/cacti " + cacti_args.join(" ")
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IO.popen(cacti_cmd) { |pipe|
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str1 = pipe.readline
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str2 = pipe.readline
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results = str2.split(", ")
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if results.size != 61
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print "CACTI ERROR: CACTI produced unexpected output.\n"
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print "Are you using the version shipped with libruby?\n"
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raise Exception
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end
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latency_ns = results[5].to_f
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if (latency_ns == "1e+39")
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print "CACTI ERROR: CACTI was unable to realistically model the cache ",@obj_name,"\n"
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print "Either change the cache parameters or manually set the latency values\n"
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raise Exception
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end
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clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6))
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latency_cycles = (latency_ns / clk_period_ns).ceil
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@latency = latency_cycles
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}
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# IO.popen(cacti_cmd) { |pipe|
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# str1 = pipe.readline
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# str2 = pipe.readline
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# results = str2.split(", ")
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# if results.size != 61
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# print "CACTI ERROR: CACTI produced unexpected output.\n"
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# print "Are you using the version shipped with libruby?\n"
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# raise Exception
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# end
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# latency_ns = results[5].to_f
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# if (latency_ns == "1e+39")
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# print "CACTI ERROR: CACTI was unable to realistically model the cache ",@obj_name,"\n"
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# print "Either change the cache parameters or manually set the latency values\n"
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# raise Exception
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# end
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# clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6))
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# latency_cycles = (latency_ns / clk_period_ns).ceil
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# @latency = latency_cycles
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# }
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elsif @latency.is_a?(Float)
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clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6))
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latency_cycles = (@latency / clk_period_ns).ceil
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@ -540,7 +539,6 @@ class MemoryControl < LibRubyObject
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end
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class Sequencer < IfacePort
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def cppClassName()
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@ -759,4 +757,5 @@ class GarnetFlexiblePipeline < GarnetNetwork
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end
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end
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#added by SS
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require "defaults.rb"
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@ -9,7 +9,7 @@ class NetPort < LibRubyObject
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# buffer_size limits the size of all other buffers connecting to
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# SLICC Controllers. When 0, infinite buffering is used.
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default_param :buffer_size, Integer, 32
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default_param :buffer_size, Integer, 0
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# added by SS for TBE
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default_param :number_of_TBEs, Integer, 256
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@ -36,7 +36,7 @@ class Debug < LibRubyObject
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# 1. change protocol_trace = true
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# 2. enable debug in the Ruby Makefile
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# 3. set start_time = 1
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default_param :protocol_trace, Boolean, false
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default_param :protocol_trace, Boolean, true
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# a string for filtering debugging output (for all g_debug vars see Debug.h)
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default_param :filter_string, String, "none"
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@ -46,9 +46,9 @@ class Debug < LibRubyObject
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# filters debugging messages based on a ruby time
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default_param :start_time, Integer, 1
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# sends debugging messages to a output filename
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default_param :output_filename, String, "none"
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default_param :output_filename, String, "debug_ss"
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end
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class Topology < LibRubyObject
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@ -71,11 +71,11 @@ end
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class Network < LibRubyObject
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default_param :endpoint_bandwidth, Integer, 10000
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default_param :adaptive_routing, Boolean, true
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default_param :number_of_virtual_networks, Integer, 6
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default_param :number_of_virtual_networks, Integer, 10
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default_param :fan_out_degree, Integer, 4
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# default buffer size. Setting to 0 indicates infinite buffering
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default_param :buffer_size, Integer, 3
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default_param :buffer_size, Integer, 0
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# local memory latency ?? NetworkLinkLatency
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default_param :link_latency, Integer, 1
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@ -204,4 +204,31 @@ class RubySystem
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default_param :profiler, Profiler, Profiler.new("profiler0")
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end
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#added by SS
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class MESI_CMP_directory_L2CacheController < CacheController
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default_param :l2_request_latency, Integer, 2
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default_param :l2_response_latency, Integer, 2
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default_param :to_L1_latency, Integer, 1
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#if 0 then automatically calculated
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default_param :lowest_bit, Integer, 0
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default_param :highest_bit, Integer, 0
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end
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class MESI_CMP_directory_L1CacheController < L1CacheController
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default_param :l1_request_latency, Integer, 2
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default_param :l1_response_latency, Integer, 2
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default_param :to_L2_latency, Integer, 1
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end
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class MESI_CMP_directory_DirectoryController < DirectoryController
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default_param :to_mem_ctrl_latency, Integer, 1
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default_param :directory_latency, Integer, 6
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end
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class MESI_CMP_directory_DMAController < DMAController
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default_param :request_latency, Integer, 6
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end
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