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ARM: Decode VFP instructions.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:00 -05:00
parent 7b8525287d
commit bc6ae010c9
4 changed files with 102 additions and 79 deletions
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70
src/arch/arm/isa/armdecode.isa
View file

@ -396,73 +396,9 @@ format DataOp {
0x7: decode OPCODE_24 {
0: decode OPCODE_4 {
0: decode CPNUM {
format FloatOp {
0x1: decode OPCODE_23_20 {
0x0: decode OPCODE_15 {
0: adf({{ Fd.sf = Fn.sf + Fm.sf; }});
1: mvf({{ Fd.sf = Fm.sf; }});
}
0x1: decode OPCODE_15 {
0: muf({{ Fd.sf = Fn.sf * Fm.sf; }});
1: mnf({{ Fd.sf = -Fm.sf; }});
}
0x2: decode OPCODE_15 {
0: suf({{ Fd.sf = Fn.sf - Fm.sf; }});
1: abs({{ Fd.sf = fabs(Fm.sf); }});
}
0x3: decode OPCODE_15 {
0: rsf({{ Fd.sf = Fm.sf - Fn.sf; }});
1: rnd({{ Fd.sf = rint(Fm.sf); }});
}
0x4: decode OPCODE_15 {
0: dvf({{ Fd.sf = Fn.sf / Fm.sf; }});
1: sqt({{ Fd.sf = sqrt(Fm.sf); }});
}
0x5: decode OPCODE_15 {
0: rdf({{ Fd.sf = Fm.sf / Fn.sf; }});
1: log({{ Fd.sf = log10(Fm.sf); }});
}
0x6: decode OPCODE_15 {
0: pow({{ Fd.sf = pow(Fm.sf, Fn.sf); }});
1: lgn({{ Fd.sf = log(Fm.sf); }});
}
0x7: decode OPCODE_15 {
0: rpw({{ Fd.sf = pow(Fn.sf, Fm.sf); }});
1: exp({{ Fd.sf = exp(Fm.sf); }});
}
0x8: decode OPCODE_15 {
0: rmf({{ Fd.sf = drem(Fn.sf, Fm.sf); }});
1: sin({{ Fd.sf = sin(Fm.sf); }});
}
0x9: decode OPCODE_15 {
0: fml({{ Fd.sf = Fn.sf * Fm.sf; }});
1: cos({{ Fd.sf = cos(Fm.sf); }});
}
0xa: decode OPCODE_15 {
0: fdv({{ Fd.sf = Fn.sf / Fm.sf; }});
1: tan({{ Fd.sf = tan(Fm.sf); }});
}
0xb: decode OPCODE_15 {
0: frd({{ Fd.sf = Fm.sf / Fn.sf; }});
1: asn({{ Fd.sf = asin(Fm.sf); }});
}
0xc: decode OPCODE_15 {
0: pol({{ Fd.sf = atan2(Fn.sf, Fm.sf); }});
1: acs({{ Fd.sf = acos(Fm.sf); }});
}
0xd: decode OPCODE_15 {
1: atn({{ Fd.sf = atan(Fm.sf); }});
}
0xe: decode OPCODE_15 {
// Unnormalised Round
1: FailUnimpl::urd();
}
0xf: decode OPCODE_15 {
// Normalise
1: FailUnimpl::nrm();
}
} // OPCODE_23_20
} // format FloatOp
0xa, 0xb: decode OPCODE_23_20 {
##include "vfpdecode.isa"
}
} // CPNUM
1: decode CPNUM { // 27-24=1110,4 ==1
1: decode OPCODE_15_12 {

26
src/arch/arm/isa/bitfields.isa
View file

@ -51,18 +51,20 @@ def bitfield OPCODE opcode;
def bitfield MEDIA_OPCODE mediaOpcode;
def bitfield MEDIA_OPCODE2 mediaOpcode2;
def bitfield USEIMM useImm;
def bitfield OPCODE_24 opcode24;
def bitfield OPCODE_24 opcode24;
def bitfield OPCODE_23_20 opcode23_20;
def bitfield OPCODE_23_21 opcode23_21;
def bitfield OPCODE_22 opcode22;
def bitfield OPCODE_20 opcode20;
def bitfield OPCODE_19 opcode19;
def bitfield OPCODE_18 opcode18;
def bitfield OPCODE_20 opcode20;
def bitfield OPCODE_19_16 opcode19_16;
def bitfield OPCODE_19 opcode19;
def bitfield OPCODE_18 opcode18;
def bitfield OPCODE_15_12 opcode15_12;
def bitfield OPCODE_15 opcode15;
def bitfield OPCODE_15 opcode15;
def bitfield MISC_OPCODE miscOpcode;
def bitfield OPC2 opc2;
def bitfield OPCODE_7 opcode7;
def bitfield OPCODE_6 opcode6;
def bitfield OPCODE_4 opcode4;
def bitfield IS_MISC isMisc;
@ -100,16 +102,16 @@ def bitfield IMMED_LO_3_0 immedLo3_0;
def bitfield IMMED_23_0 immed23_0;
def bitfield CPNUM cpNum;
def bitfield CPNUM cpNum;
// Note that FP Regs are only 3 bits
def bitfield FN fn;
def bitfield FD fd;
def bitfield FPREGIMM fpRegImm;
def bitfield FN fn;
def bitfield FD fd;
def bitfield FPREGIMM fpRegImm;
// We can just use 3:0 for FM since the hard-wired FP regs are handled in
// float_regfile.hh
def bitfield FM fm;
def bitfield FPIMM fpImm;
def bitfield PUNWL punwl;
def bitfield FM fm;
def bitfield FPIMM fpImm;
def bitfield PUNWL punwl;
// M5 instructions
def bitfield M5FUNC m5Func;

83
src/arch/arm/isa/vfpdecode.isa Normal file
View file

@ -0,0 +1,83 @@
// -*- mode:c++ -*-
// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2009 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
// There needs to be a decode statement in the file that includes this since
// the isa_parser can't handle a case and what it corresponds with spanning
// lines. it should decode bits 23 through 20.
format FloatOp {
0x0, 0x4: WarnUnimpl::vmla(); // vmls
0x1, 0x5: WarnUnimpl::vnmla(); // vnmls, vnmul
0x2, 0x6: decode OPCODE_6 {
0x0: WarnUnimpl::vmul();
0x1: WarnUnimpl::vnmla(); // vnmls, vnmul
}
0x3, 0x7: decode OPCODE_6 {
0x0: WarnUnimpl::vadd();
0x1: WarnUnimpl::vsub();
}
0x8, 0xc: WarnUnimpl::vdiv();
0xb, 0xf: decode OPCODE_6 {
0x0: WarnUnimpl::vmov(); // immediate
0x1: decode OPCODE_19_16 {
0x0: decode OPCODE_7 {
0x0: WarnUnimpl::vmov(); // register
0x1: WarnUnimpl::vabs();
}
0x1: decode OPCODE_7 {
0x0: WarnUnimpl::vneg();
0x1: WarnUnimpl::vsqrt();
}
0x2, 0x3: WarnUnimpl::vcvtb(); // vcvtt
0x4, 0x5: WarnUnimpl::vcmp(); // vcmpe double to single
0x7: decode OPCODE_7 {
0x0: WarnUnimpl::vcvt(); // double and single
}
0x8: WarnUnimpl::vcvt(); // vcvtr fp and int
0xa, 0xb: WarnUnimpl::vcvt(); // fp and fixed point
0xc, 0xd: WarnUnimpl::vcvt(); // vcvtr fp and int
0xe, 0xf: WarnUnimpl::vcvt(); // fp and fixed point
}
}
}

2
src/arch/arm/types.hh
View file

@ -71,6 +71,7 @@ namespace ArmISA
Bitfield<23, 21> opcode23_21;
Bitfield<20> opcode20;
Bitfield<22> opcode22;
Bitfield<19, 16> opcode19_16;
Bitfield<19> opcode19;
Bitfield<18> opcode18;
Bitfield<15, 12> opcode15_12;
@ -78,6 +79,7 @@ namespace ArmISA
Bitfield<7, 4> miscOpcode;
Bitfield<7,5> opc2;
Bitfield<7> opcode7;
Bitfield<6> opcode6;
Bitfield<4> opcode4;
Bitfield<31, 28> condCode;