ruby: MOESI_CMP_directory updated to the new config system
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6 changed files with 258 additions and 129 deletions
151
configs/ruby/MOESI_CMP_directory.py
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151
configs/ruby/MOESI_CMP_directory.py
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@ -0,0 +1,151 @@
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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import math
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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#
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# Note: the L1 Cache latency is only used by the sequencer on fast path hits
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#
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class L1Cache(RubyCache):
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latency = 3
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#
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# Note: the L2 Cache latency is not currently used
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#
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class L2Cache(RubyCache):
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latency = 15
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def create_system(options, phys_mem, piobus, dma_devices):
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if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
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panic("This script requires the MOESI_CMP_directory protocol to be built.")
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cpu_sequencers = []
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#
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# The ruby network creation expects the list of nodes in the system to be
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# consistent with the NetDest list. Therefore the l1 controller nodes must be
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# listed before the directory nodes and directory nodes before dma nodes, etc.
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#
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l1_cntrl_nodes = []
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l2_cntrl_nodes = []
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dir_cntrl_nodes = []
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dma_cntrl_nodes = []
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#
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# Must create the individual controllers before the network to ensure the
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# controller constructors are called before the network constructor
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#
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for i in xrange(options.num_cpus):
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#
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# First create the Ruby objects associated with this cpu
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#
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l1i_cache = L1Cache(size = options.l1i_size,
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assoc = options.l1i_assoc)
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l1d_cache = L1Cache(size = options.l1d_size,
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assoc = options.l1d_assoc)
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cpu_seq = RubySequencer(icache = l1i_cache,
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dcache = l1d_cache,
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physMemPort = phys_mem.port,
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physmem = phys_mem)
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if piobus != None:
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cpu_seq.pio_port = piobus.port
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l1_cntrl = L1Cache_Controller(version = i,
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sequencer = cpu_seq,
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L1IcacheMemory = l1i_cache,
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L1DcacheMemory = l1d_cache,
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l2_select_num_bits = \
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math.log(options.num_l2caches, 2))
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#
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# Add controllers and sequencers to the appropriate lists
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#
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cpu_sequencers.append(cpu_seq)
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l1_cntrl_nodes.append(l1_cntrl)
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for i in xrange(options.num_l2caches):
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#
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# First create the Ruby objects associated with this cpu
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#
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l2_cache = L2Cache(size = options.l2_size,
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assoc = options.l2_assoc)
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l2_cntrl = L2Cache_Controller(version = i,
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L2cacheMemory = l2_cache)
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l2_cntrl_nodes.append(l2_cntrl)
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phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
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mem_module_size = phys_mem_size / options.num_dirs
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for i in xrange(options.num_dirs):
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#
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# Create the Ruby objects associated with the directory controller
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#
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mem_cntrl = RubyMemoryControl(version = i)
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dir_size = MemorySize('0B')
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dir_size.value = mem_module_size
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dir_cntrl = Directory_Controller(version = i,
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directory = \
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RubyDirectoryMemory(version = i,
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size = dir_size),
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memBuffer = mem_cntrl)
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dir_cntrl_nodes.append(dir_cntrl)
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for i, dma_device in enumerate(dma_devices):
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#
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# Create the Ruby objects associated with the dma controller
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#
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dma_seq = DMASequencer(version = i,
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physMemPort = phys_mem.port,
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physmem = phys_mem)
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dma_cntrl = DMA_Controller(version = i,
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dma_sequencer = dma_seq)
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dma_cntrl.dma_sequencer.port = dma_device.dma
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dma_cntrl_nodes.append(dma_cntrl)
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all_cntrls = l1_cntrl_nodes + \
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l2_cntrl_nodes + \
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dir_cntrl_nodes + \
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dma_cntrl_nodes
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return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
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@ -33,6 +33,7 @@ from m5.defines import buildEnv
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from m5.util import addToPath
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import MOESI_hammer
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import MOESI_CMP_directory
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import MI_example
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import MOESI_CMP_token
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@ -46,6 +47,12 @@ def create_system(options, physmem, piobus = None, dma_devices = []):
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physmem, \
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piobus, \
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dma_devices)
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elif protocol == "MOESI_CMP_directory":
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(cpu_sequencers, dir_cntrls, all_cntrls) = \
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MOESI_CMP_directory.create_system(options, \
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physmem, \
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piobus, \
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dma_devices)
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elif protocol == "MI_example":
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(cpu_sequencers, dir_cntrls, all_cntrls) = \
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MI_example.create_system(options, \
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@ -33,9 +33,11 @@
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*/
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machine(L1Cache, "Directory protocol")
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: int request_latency,
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int l2_select_low_bit,
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int l2_select_num_bits
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: Sequencer * sequencer,
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CacheMemory * L1IcacheMemory,
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CacheMemory * L1DcacheMemory,
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int l2_select_num_bits,
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int request_latency = 2
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{
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// NODE L1 CACHE
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@ -127,16 +129,6 @@ machine(L1Cache, "Directory protocol")
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int NumPendingMsgs, default="0", desc="Number of acks/data messages that this processor is waiting for";
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}
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external_type(CacheMemory) {
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bool cacheAvail(Address);
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Address cacheProbe(Address);
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void allocate(Address, Entry);
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void deallocate(Address);
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Entry lookup(Address);
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void changePermission(Address, AccessPermission);
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bool isTagPresent(Address);
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}
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external_type(TBETable) {
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TBE lookup(Address);
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void allocate(Address);
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@ -146,18 +138,16 @@ machine(L1Cache, "Directory protocol")
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MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
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Sequencer sequencer, factory='RubySystem::getSequencer(m_cfg["sequencer"])';
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TBETable TBEs, template_hack="<L1Cache_TBE>";
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CacheMemory L1IcacheMemory, factory='RubySystem::getCache(m_cfg["icache"])';
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CacheMemory L1DcacheMemory, factory='RubySystem::getCache(m_cfg["dcache"])';
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TimerTable useTimerTable;
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int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
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Entry getCacheEntry(Address addr), return_by_ref="yes" {
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if (L1DcacheMemory.isTagPresent(addr)) {
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return L1DcacheMemory[addr];
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return static_cast(Entry, L1DcacheMemory[addr]);
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} else {
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return L1IcacheMemory[addr];
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return static_cast(Entry, L1IcacheMemory[addr]);
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}
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}
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@ -33,8 +33,9 @@
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*/
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machine(L2Cache, "Token protocol")
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: int response_latency,
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int request_latency
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: CacheMemory * L2cacheMemory,
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int response_latency = 2,
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int request_latency = 2
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{
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// L2 BANK QUEUES
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bool isPresent(Address);
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}
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external_type(CacheMemory) {
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bool cacheAvail(Address);
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Address cacheProbe(Address);
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void allocate(Address, Entry);
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void deallocate(Address);
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Entry lookup(Address);
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void changePermission(Address, AccessPermission);
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bool isTagPresent(Address);
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void setMRU(Address);
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}
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external_type(PerfectCacheMemory) {
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void allocate(Address);
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void deallocate(Address);
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@ -229,15 +219,14 @@ machine(L2Cache, "Token protocol")
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TBETable L2_TBEs, template_hack="<L2Cache_TBE>";
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CacheMemory L2cacheMemory, factory='RubySystem::getCache(m_cfg["cache"])';
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PerfectCacheMemory localDirectory, template_hack="<L2Cache_DirEntry>";
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Entry getL2CacheEntry(Address addr), return_by_ref="yes" {
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if (L2cacheMemory.isTagPresent(addr)) {
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return L2cacheMemory[addr];
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return static_cast(Entry, L2cacheMemory[addr]);
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} else {
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return L2cacheMemory[addr];
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return static_cast(Entry, L2cacheMemory[addr]);
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}
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}
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@ -258,11 +247,11 @@ machine(L2Cache, "Token protocol")
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bool isOnlySharer(Address addr, MachineID shar_id) {
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if (isCacheTagPresent(addr)) {
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assert (localDirectory.isTagPresent(addr) == false);
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if (L2cacheMemory[addr].Sharers.count() > 1) {
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if (getL2CacheEntry(addr).Sharers.count() > 1) {
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return false;
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}
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else if (L2cacheMemory[addr].Sharers.count() == 1) {
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if (L2cacheMemory[addr].Sharers.isElement(shar_id)) {
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else if (getL2CacheEntry(addr).Sharers.count() == 1) {
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if (getL2CacheEntry(addr).Sharers.isElement(shar_id)) {
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return true;
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}
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else {
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void copyCacheStateToDir(Address addr) {
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assert(localDirectory.isTagPresent(addr) == false);
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localDirectory.allocate(addr);
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localDirectory[addr].DirState := L2cacheMemory[addr].CacheState;
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localDirectory[addr].Sharers := L2cacheMemory[addr].Sharers;
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localDirectory[addr].Owner := L2cacheMemory[addr].Owner;
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localDirectory[addr].OwnerValid := L2cacheMemory[addr].OwnerValid;
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localDirectory[addr].DirState := getL2CacheEntry(addr).CacheState;
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localDirectory[addr].Sharers := getL2CacheEntry(addr).Sharers;
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localDirectory[addr].Owner := getL2CacheEntry(addr).Owner;
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localDirectory[addr].OwnerValid := getL2CacheEntry(addr).OwnerValid;
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}
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void copyDirToCache(Address addr) {
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L2cacheMemory[addr].Sharers := localDirectory[addr].Sharers;
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L2cacheMemory[addr].Owner := localDirectory[addr].Owner;
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L2cacheMemory[addr].OwnerValid := localDirectory[addr].OwnerValid;
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getL2CacheEntry(addr).Sharers := localDirectory[addr].Sharers;
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getL2CacheEntry(addr).Owner := localDirectory[addr].Owner;
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getL2CacheEntry(addr).OwnerValid := localDirectory[addr].OwnerValid;
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}
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void recordLocalSharerInDir(Address addr, MachineID shar_id) {
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if (isCacheTagPresent(addr)) {
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assert (localDirectory.isTagPresent(addr) == false);
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L2cacheMemory[addr].Sharers.add(shar_id);
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getL2CacheEntry(addr).Sharers.add(shar_id);
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}
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else {
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if (localDirectory.isTagPresent(addr) == false) {
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@ -332,9 +321,9 @@ machine(L2Cache, "Token protocol")
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if (isCacheTagPresent(addr)) {
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assert (localDirectory.isTagPresent(addr) == false);
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L2cacheMemory[addr].Sharers.clear();
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L2cacheMemory[addr].OwnerValid := true;
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L2cacheMemory[addr].Owner := exc_id;
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getL2CacheEntry(addr).Sharers.clear();
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getL2CacheEntry(addr).OwnerValid := true;
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getL2CacheEntry(addr).Owner := exc_id;
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}
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else {
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if (localDirectory.isTagPresent(addr) == false) {
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@ -350,8 +339,8 @@ machine(L2Cache, "Token protocol")
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void removeAllLocalSharersFromDir(Address addr) {
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if (isCacheTagPresent(addr)) {
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assert (localDirectory.isTagPresent(addr) == false);
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L2cacheMemory[addr].Sharers.clear();
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L2cacheMemory[addr].OwnerValid := false;
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getL2CacheEntry(addr).Sharers.clear();
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getL2CacheEntry(addr).OwnerValid := false;
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}
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else {
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localDirectory[addr].Sharers.clear();
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@ -362,7 +351,7 @@ machine(L2Cache, "Token protocol")
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void removeSharerFromDir(Address addr, MachineID sender) {
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if (isCacheTagPresent(addr)) {
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assert (localDirectory.isTagPresent(addr) == false);
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L2cacheMemory[addr].Sharers.remove(sender);
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getL2CacheEntry(addr).Sharers.remove(sender);
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}
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else {
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localDirectory[addr].Sharers.remove(sender);
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@ -372,7 +361,7 @@ machine(L2Cache, "Token protocol")
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void removeOwnerFromDir(Address addr, MachineID sender) {
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if (isCacheTagPresent(addr)) {
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assert (localDirectory.isTagPresent(addr) == false);
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L2cacheMemory[addr].OwnerValid := false;
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getL2CacheEntry(addr).OwnerValid := false;
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}
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else {
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localDirectory[addr].OwnerValid := false;
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@ -382,7 +371,7 @@ machine(L2Cache, "Token protocol")
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bool isLocalSharer(Address addr, MachineID shar_id) {
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if (isCacheTagPresent(addr)) {
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assert (localDirectory.isTagPresent(addr) == false);
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return L2cacheMemory[addr].Sharers.isElement(shar_id);
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return getL2CacheEntry(addr).Sharers.isElement(shar_id);
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}
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else {
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return localDirectory[addr].Sharers.isElement(shar_id);
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@ -393,7 +382,7 @@ machine(L2Cache, "Token protocol")
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NetDest getLocalSharers(Address addr) {
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if (isCacheTagPresent(addr)) {
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assert (localDirectory.isTagPresent(addr) == false);
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return L2cacheMemory[addr].Sharers;
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return getL2CacheEntry(addr).Sharers;
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}
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else {
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return localDirectory[addr].Sharers;
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@ -404,7 +393,7 @@ machine(L2Cache, "Token protocol")
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MachineID getLocalOwner(Address addr) {
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if (isCacheTagPresent(addr)) {
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assert (localDirectory.isTagPresent(addr) == false);
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return L2cacheMemory[addr].Owner;
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return getL2CacheEntry(addr).Owner;
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}
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else {
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return localDirectory[addr].Owner;
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@ -416,7 +405,7 @@ machine(L2Cache, "Token protocol")
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int countLocalSharers(Address addr) {
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if (isCacheTagPresent(addr)) {
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assert (localDirectory.isTagPresent(addr) == false);
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return L2cacheMemory[addr].Sharers.count();
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return getL2CacheEntry(addr).Sharers.count();
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}
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else {
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return localDirectory[addr].Sharers.count();
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@ -426,7 +415,7 @@ machine(L2Cache, "Token protocol")
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bool isLocalOwnerValid(Address addr) {
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if (isCacheTagPresent(addr)) {
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assert (localDirectory.isTagPresent(addr) == false);
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return L2cacheMemory[addr].OwnerValid;
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return getL2CacheEntry(addr).OwnerValid;
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}
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else {
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return localDirectory[addr].OwnerValid;
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@ -436,11 +425,11 @@ machine(L2Cache, "Token protocol")
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int countLocalSharersExceptRequestor(Address addr, MachineID requestor) {
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if (isCacheTagPresent(addr)) {
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assert (localDirectory.isTagPresent(addr) == false);
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if (L2cacheMemory[addr].Sharers.isElement(requestor)) {
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return ( L2cacheMemory[addr].Sharers.count() - 1 );
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if (getL2CacheEntry(addr).Sharers.isElement(requestor)) {
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return ( getL2CacheEntry(addr).Sharers.count() - 1 );
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}
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else {
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return L2cacheMemory[addr].Sharers.count();
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return getL2CacheEntry(addr).Sharers.count();
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}
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}
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else {
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@ -32,7 +32,9 @@
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*/
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machine(Directory, "Directory protocol")
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: int directory_latency
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: DirectoryMemory * directory,
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MemoryControl * memBuffer,
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int directory_latency = 6
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{
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// ** IN QUEUES **
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|
@ -92,7 +94,7 @@ machine(Directory, "Directory protocol")
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// TYPES
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// DirectoryEntry
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structure(Entry, desc="...") {
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structure(Entry, desc="...", interface='AbstractEntry') {
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State DirectoryState, desc="Directory state";
|
||||
DataBlock DataBlk, desc="data for the block";
|
||||
NetDest Sharers, desc="Sharers for this block";
|
||||
|
@ -107,11 +109,6 @@ machine(Directory, "Directory protocol")
|
|||
MachineID Requestor, desc="original requestor";
|
||||
}
|
||||
|
||||
external_type(DirectoryMemory) {
|
||||
Entry lookup(Address);
|
||||
bool isPresent(Address);
|
||||
}
|
||||
|
||||
external_type(TBETable) {
|
||||
TBE lookup(Address);
|
||||
void allocate(Address);
|
||||
|
@ -119,55 +116,50 @@ machine(Directory, "Directory protocol")
|
|||
bool isPresent(Address);
|
||||
}
|
||||
|
||||
// to simulate detailed DRAM
|
||||
external_type(MemoryControl, inport="yes", outport="yes") {
|
||||
|
||||
}
|
||||
|
||||
|
||||
// ** OBJECTS **
|
||||
|
||||
DirectoryMemory directory, factory='RubySystem::getDirectory(m_cfg["directory"])';
|
||||
MemoryControl memBuffer, factory='RubySystem::getMemoryControl(m_cfg["memory_control"])';
|
||||
TBETable TBEs, template_hack="<Directory_TBE>";
|
||||
|
||||
Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
|
||||
return static_cast(Entry, directory[addr]);
|
||||
}
|
||||
|
||||
State getState(Address addr) {
|
||||
return directory[addr].DirectoryState;
|
||||
return getDirectoryEntry(addr).DirectoryState;
|
||||
}
|
||||
|
||||
void setState(Address addr, State state) {
|
||||
if (directory.isPresent(addr)) {
|
||||
|
||||
if (state == State:I) {
|
||||
assert(directory[addr].Owner.count() == 0);
|
||||
assert(directory[addr].Sharers.count() == 0);
|
||||
assert(getDirectoryEntry(addr).Owner.count() == 0);
|
||||
assert(getDirectoryEntry(addr).Sharers.count() == 0);
|
||||
}
|
||||
|
||||
if (state == State:S) {
|
||||
assert(directory[addr].Owner.count() == 0);
|
||||
assert(getDirectoryEntry(addr).Owner.count() == 0);
|
||||
}
|
||||
|
||||
if (state == State:O) {
|
||||
assert(directory[addr].Owner.count() == 1);
|
||||
assert(directory[addr].Sharers.isSuperset(directory[addr].Owner) == false);
|
||||
assert(getDirectoryEntry(addr).Owner.count() == 1);
|
||||
assert(getDirectoryEntry(addr).Sharers.isSuperset(getDirectoryEntry(addr).Owner) == false);
|
||||
}
|
||||
|
||||
if (state == State:M) {
|
||||
assert(directory[addr].Owner.count() == 1);
|
||||
assert(directory[addr].Sharers.count() == 0);
|
||||
assert(getDirectoryEntry(addr).Owner.count() == 1);
|
||||
assert(getDirectoryEntry(addr).Sharers.count() == 0);
|
||||
}
|
||||
|
||||
if ((state != State:SS) && (state != State:OO)) {
|
||||
assert(directory[addr].WaitingUnblocks == 0);
|
||||
assert(getDirectoryEntry(addr).WaitingUnblocks == 0);
|
||||
}
|
||||
|
||||
if ( (directory[addr].DirectoryState != State:I) && (state == State:I) ) {
|
||||
directory[addr].DirectoryState := state;
|
||||
if ( (getDirectoryEntry(addr).DirectoryState != State:I) && (state == State:I) ) {
|
||||
getDirectoryEntry(addr).DirectoryState := state;
|
||||
// disable coherence checker
|
||||
// sequencer.checkCoherence(addr);
|
||||
}
|
||||
else {
|
||||
directory[addr].DirectoryState := state;
|
||||
getDirectoryEntry(addr).DirectoryState := state;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -175,7 +167,7 @@ machine(Directory, "Directory protocol")
|
|||
// if no sharers, then directory can be considered both a sharer and exclusive w.r.t. coherence checking
|
||||
bool isBlockShared(Address addr) {
|
||||
if (directory.isPresent(addr)) {
|
||||
if (directory[addr].DirectoryState == State:I) {
|
||||
if (getDirectoryEntry(addr).DirectoryState == State:I) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
@ -184,7 +176,7 @@ machine(Directory, "Directory protocol")
|
|||
|
||||
bool isBlockExclusive(Address addr) {
|
||||
if (directory.isPresent(addr)) {
|
||||
if (directory[addr].DirectoryState == State:I) {
|
||||
if (getDirectoryEntry(addr).DirectoryState == State:I) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
@ -211,7 +203,7 @@ machine(Directory, "Directory protocol")
|
|||
if (unblockNetwork_in.isReady()) {
|
||||
peek(unblockNetwork_in, ResponseMsg) {
|
||||
if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
|
||||
if (directory[in_msg.Address].WaitingUnblocks == 1) {
|
||||
if (getDirectoryEntry(in_msg.Address).WaitingUnblocks == 1) {
|
||||
trigger(Event:Last_Unblock, in_msg.Address);
|
||||
} else {
|
||||
trigger(Event:Unblock, in_msg.Address);
|
||||
|
@ -298,16 +290,16 @@ machine(Directory, "Directory protocol")
|
|||
}
|
||||
|
||||
action(c_clearOwner, "c", desc="Clear the owner field") {
|
||||
directory[address].Owner.clear();
|
||||
getDirectoryEntry(address).Owner.clear();
|
||||
}
|
||||
|
||||
action(c_moveOwnerToSharer, "cc", desc="Move owner to sharers") {
|
||||
directory[address].Sharers.addNetDest(directory[address].Owner);
|
||||
directory[address].Owner.clear();
|
||||
getDirectoryEntry(address).Sharers.addNetDest(getDirectoryEntry(address).Owner);
|
||||
getDirectoryEntry(address).Owner.clear();
|
||||
}
|
||||
|
||||
action(cc_clearSharers, "\c", desc="Clear the sharers field") {
|
||||
directory[address].Sharers.clear();
|
||||
getDirectoryEntry(address).Sharers.clear();
|
||||
}
|
||||
|
||||
action(d_sendDataMsg, "d", desc="Send data to requestor") {
|
||||
|
@ -317,7 +309,7 @@ machine(Directory, "Directory protocol")
|
|||
out_msg.Sender := machineID;
|
||||
out_msg.SenderMachine := MachineType:Directory;
|
||||
out_msg.Destination.add(in_msg.OriginalRequestorMachId);
|
||||
//out_msg.DataBlk := directory[in_msg.Address].DataBlk;
|
||||
//out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
|
||||
out_msg.DataBlk := in_msg.DataBlk;
|
||||
out_msg.Dirty := false; // By definition, the block is now clean
|
||||
out_msg.Acks := in_msg.Acks;
|
||||
|
@ -338,7 +330,7 @@ machine(Directory, "Directory protocol")
|
|||
out_msg.Sender := machineID;
|
||||
out_msg.SenderMachine := MachineType:Directory;
|
||||
out_msg.Destination.add(in_msg.Requestor);
|
||||
out_msg.DataBlk := directory[in_msg.Address].DataBlk;
|
||||
out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
|
||||
out_msg.Dirty := false; // By definition, the block is now clean
|
||||
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
|
||||
out_msg.MessageSize := MessageSizeType:Response_Data;
|
||||
|
@ -350,8 +342,8 @@ machine(Directory, "Directory protocol")
|
|||
|
||||
action(e_ownerIsUnblocker, "e", desc="The owner is now the unblocker") {
|
||||
peek(unblockNetwork_in, ResponseMsg) {
|
||||
directory[address].Owner.clear();
|
||||
directory[address].Owner.add(in_msg.Sender);
|
||||
getDirectoryEntry(address).Owner.clear();
|
||||
getDirectoryEntry(address).Owner.add(in_msg.Sender);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -361,9 +353,9 @@ machine(Directory, "Directory protocol")
|
|||
out_msg.Address := address;
|
||||
out_msg.Type := in_msg.Type;
|
||||
out_msg.Requestor := in_msg.Requestor;
|
||||
out_msg.Destination.addNetDest(directory[in_msg.Address].Owner);
|
||||
out_msg.Acks := directory[address].Sharers.count();
|
||||
if (directory[address].Sharers.isElement(in_msg.Requestor)) {
|
||||
out_msg.Destination.addNetDest(getDirectoryEntry(in_msg.Address).Owner);
|
||||
out_msg.Acks := getDirectoryEntry(address).Sharers.count();
|
||||
if (getDirectoryEntry(address).Sharers.isElement(in_msg.Requestor)) {
|
||||
out_msg.Acks := out_msg.Acks - 1;
|
||||
}
|
||||
out_msg.MessageSize := MessageSizeType:Forwarded_Control;
|
||||
|
@ -377,9 +369,9 @@ machine(Directory, "Directory protocol")
|
|||
out_msg.Address := address;
|
||||
out_msg.Type := in_msg.Type;
|
||||
out_msg.Requestor := machineID;
|
||||
out_msg.Destination.addNetDest(directory[in_msg.Address].Owner);
|
||||
out_msg.Acks := directory[address].Sharers.count();
|
||||
if (directory[address].Sharers.isElement(in_msg.Requestor)) {
|
||||
out_msg.Destination.addNetDest(getDirectoryEntry(in_msg.Address).Owner);
|
||||
out_msg.Acks := getDirectoryEntry(address).Sharers.count();
|
||||
if (getDirectoryEntry(address).Sharers.isElement(in_msg.Requestor)) {
|
||||
out_msg.Acks := out_msg.Acks - 1;
|
||||
}
|
||||
out_msg.MessageSize := MessageSizeType:Forwarded_Control;
|
||||
|
@ -389,14 +381,14 @@ machine(Directory, "Directory protocol")
|
|||
|
||||
action(g_sendInvalidations, "g", desc="Send invalidations to sharers, not including the requester") {
|
||||
peek(requestQueue_in, RequestMsg) {
|
||||
if ((directory[in_msg.Address].Sharers.count() > 1) ||
|
||||
((directory[in_msg.Address].Sharers.count() > 0) && (directory[in_msg.Address].Sharers.isElement(in_msg.Requestor) == false))) {
|
||||
if ((getDirectoryEntry(in_msg.Address).Sharers.count() > 1) ||
|
||||
((getDirectoryEntry(in_msg.Address).Sharers.count() > 0) && (getDirectoryEntry(in_msg.Address).Sharers.isElement(in_msg.Requestor) == false))) {
|
||||
enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) {
|
||||
out_msg.Address := address;
|
||||
out_msg.Type := CoherenceRequestType:INV;
|
||||
out_msg.Requestor := in_msg.Requestor;
|
||||
// out_msg.Destination := directory[in_msg.Address].Sharers;
|
||||
out_msg.Destination.addNetDest(directory[in_msg.Address].Sharers);
|
||||
// out_msg.Destination := getDirectoryEntry(in_msg.Address).Sharers;
|
||||
out_msg.Destination.addNetDest(getDirectoryEntry(in_msg.Address).Sharers);
|
||||
out_msg.Destination.remove(in_msg.Requestor);
|
||||
out_msg.MessageSize := MessageSizeType:Invalidate_Control;
|
||||
}
|
||||
|
@ -416,7 +408,7 @@ machine(Directory, "Directory protocol")
|
|||
peek(unblockNetwork_in, ResponseMsg) {
|
||||
assert(in_msg.Dirty);
|
||||
assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
|
||||
directory[in_msg.Address].DataBlk := in_msg.DataBlk;
|
||||
getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
|
||||
DEBUG_EXPR(in_msg.Address);
|
||||
DEBUG_EXPR(in_msg.DataBlk);
|
||||
}
|
||||
|
@ -424,7 +416,7 @@ machine(Directory, "Directory protocol")
|
|||
|
||||
action(p_writeFwdDataToMemory, "p", desc="Write Response data to memory") {
|
||||
peek(unblockNetwork_in, ResponseMsg) {
|
||||
directory[in_msg.Address].DataBlk := in_msg.DataBlk;
|
||||
getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
|
||||
DEBUG_EXPR(in_msg.Address);
|
||||
DEBUG_EXPR(in_msg.DataBlk);
|
||||
}
|
||||
|
@ -439,23 +431,23 @@ machine(Directory, "Directory protocol")
|
|||
// implementation. We include the data in the "dataless"
|
||||
// message so we can assert the clean data matches the datablock
|
||||
// in memory
|
||||
assert(directory[in_msg.Address].DataBlk == in_msg.DataBlk);
|
||||
assert(getDirectoryEntry(in_msg.Address).DataBlk == in_msg.DataBlk);
|
||||
}
|
||||
}
|
||||
|
||||
action(m_addUnlockerToSharers, "m", desc="Add the unlocker to the sharer list") {
|
||||
peek(unblockNetwork_in, ResponseMsg) {
|
||||
directory[address].Sharers.add(in_msg.Sender);
|
||||
getDirectoryEntry(address).Sharers.add(in_msg.Sender);
|
||||
}
|
||||
}
|
||||
|
||||
action(n_incrementOutstanding, "n", desc="Increment outstanding requests") {
|
||||
directory[address].WaitingUnblocks := directory[address].WaitingUnblocks + 1;
|
||||
getDirectoryEntry(address).WaitingUnblocks := getDirectoryEntry(address).WaitingUnblocks + 1;
|
||||
}
|
||||
|
||||
action(o_decrementOutstanding, "o", desc="Decrement outstanding requests") {
|
||||
directory[address].WaitingUnblocks := directory[address].WaitingUnblocks - 1;
|
||||
assert(directory[address].WaitingUnblocks >= 0);
|
||||
getDirectoryEntry(address).WaitingUnblocks := getDirectoryEntry(address).WaitingUnblocks - 1;
|
||||
assert(getDirectoryEntry(address).WaitingUnblocks >= 0);
|
||||
}
|
||||
|
||||
action(q_popMemQueue, "q", desc="Pop off-chip request queue") {
|
||||
|
@ -469,13 +461,13 @@ machine(Directory, "Directory protocol")
|
|||
out_msg.Type := MemoryRequestType:MEMORY_READ;
|
||||
out_msg.Sender := machineID;
|
||||
out_msg.OriginalRequestorMachId := in_msg.Requestor;
|
||||
out_msg.DataBlk := directory[in_msg.Address].DataBlk;
|
||||
out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
|
||||
out_msg.MessageSize := in_msg.MessageSize;
|
||||
//out_msg.Prefetch := false;
|
||||
// These are not used by memory but are passed back here with the read data:
|
||||
out_msg.ReadX := (in_msg.Type == CoherenceRequestType:GETS && directory[address].Sharers.count() == 0);
|
||||
out_msg.Acks := directory[address].Sharers.count();
|
||||
if (directory[address].Sharers.isElement(in_msg.Requestor)) {
|
||||
out_msg.ReadX := (in_msg.Type == CoherenceRequestType:GETS && getDirectoryEntry(address).Sharers.count() == 0);
|
||||
out_msg.Acks := getDirectoryEntry(address).Sharers.count();
|
||||
if (getDirectoryEntry(address).Sharers.isElement(in_msg.Requestor)) {
|
||||
out_msg.Acks := out_msg.Acks - 1;
|
||||
}
|
||||
DEBUG_EXPR(out_msg);
|
||||
|
@ -497,7 +489,7 @@ machine(Directory, "Directory protocol")
|
|||
//out_msg.Prefetch := false;
|
||||
// Not used:
|
||||
out_msg.ReadX := false;
|
||||
out_msg.Acks := directory[address].Sharers.count(); // for dma requests
|
||||
out_msg.Acks := getDirectoryEntry(address).Sharers.count(); // for dma requests
|
||||
DEBUG_EXPR(out_msg);
|
||||
}
|
||||
}
|
||||
|
@ -515,7 +507,7 @@ machine(Directory, "Directory protocol")
|
|||
//out_msg.Prefetch := false;
|
||||
// Not used:
|
||||
out_msg.ReadX := false;
|
||||
out_msg.Acks := directory[address].Sharers.count(); // for dma requests
|
||||
out_msg.Acks := getDirectoryEntry(address).Sharers.count(); // for dma requests
|
||||
DEBUG_EXPR(out_msg);
|
||||
}
|
||||
}
|
||||
|
@ -538,7 +530,7 @@ machine(Directory, "Directory protocol")
|
|||
out_msg.SenderMachine := MachineType:Directory;
|
||||
out_msg.Destination.add(in_msg.Requestor);
|
||||
out_msg.DataBlk := in_msg.DataBlk;
|
||||
out_msg.Acks := directory[address].Sharers.count(); // for dma requests
|
||||
out_msg.Acks := getDirectoryEntry(address).Sharers.count(); // for dma requests
|
||||
out_msg.Type := CoherenceResponseType:DMA_ACK;
|
||||
out_msg.MessageSize := MessageSizeType:Writeback_Control;
|
||||
}
|
||||
|
@ -555,7 +547,7 @@ machine(Directory, "Directory protocol")
|
|||
out_msg.Destination.add(TBEs[address].Requestor);
|
||||
}
|
||||
out_msg.DataBlk := in_msg.DataBlk;
|
||||
out_msg.Acks := directory[address].Sharers.count(); // for dma requests
|
||||
out_msg.Acks := getDirectoryEntry(address).Sharers.count(); // for dma requests
|
||||
out_msg.Type := CoherenceResponseType:DMA_ACK;
|
||||
out_msg.MessageSize := MessageSizeType:Writeback_Control;
|
||||
}
|
||||
|
@ -564,12 +556,12 @@ machine(Directory, "Directory protocol")
|
|||
|
||||
action(l_writeDMADataToMemory, "\l", desc="Write data from a DMA_WRITE to memory") {
|
||||
peek(requestQueue_in, RequestMsg) {
|
||||
directory[address].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
|
||||
getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
|
||||
}
|
||||
}
|
||||
|
||||
action(l_writeDMADataToMemoryFromTBE, "\ll", desc="Write data from a DMA_WRITE to memory") {
|
||||
directory[address].DataBlk.copyPartial(TBEs[address].DataBlk,
|
||||
getDirectoryEntry(address).DataBlk.copyPartial(TBEs[address].DataBlk,
|
||||
addressOffset(TBEs[address].PhysicalAddress),
|
||||
TBEs[address].Len);
|
||||
}
|
||||
|
|
|
@ -1,7 +1,8 @@
|
|||
|
||||
machine(DMA, "DMA Controller")
|
||||
: int request_latency,
|
||||
int response_latency
|
||||
: DMASequencer * dma_sequencer,
|
||||
int request_latency = 14,
|
||||
int response_latency = 14
|
||||
{
|
||||
|
||||
MessageBuffer goo1, network="From", virtual_network="0", ordered="false";
|
||||
|
@ -47,7 +48,6 @@ machine(DMA, "DMA Controller")
|
|||
|
||||
MessageBuffer mandatoryQueue, ordered="false";
|
||||
MessageBuffer triggerQueue, ordered="true";
|
||||
DMASequencer dma_sequencer, factory='RubySystem::getDMASequencer(m_cfg["dma_sequencer"])';
|
||||
TBETable TBEs, template_hack="<DMA_TBE>";
|
||||
State cur_state;
|
||||
|
||||
|
|
Loading…
Reference in a new issue