diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py new file mode 100644 index 000000000..6e248573d --- /dev/null +++ b/configs/ruby/MOESI_CMP_directory.py @@ -0,0 +1,151 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2009 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Brad Beckmann + +import math +import m5 +from m5.objects import * +from m5.defines import buildEnv +from m5.util import addToPath + +# +# Note: the L1 Cache latency is only used by the sequencer on fast path hits +# +class L1Cache(RubyCache): + latency = 3 + +# +# Note: the L2 Cache latency is not currently used +# +class L2Cache(RubyCache): + latency = 15 + +def create_system(options, phys_mem, piobus, dma_devices): + + if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': + panic("This script requires the MOESI_CMP_directory protocol to be built.") + + cpu_sequencers = [] + + # + # The ruby network creation expects the list of nodes in the system to be + # consistent with the NetDest list. Therefore the l1 controller nodes must be + # listed before the directory nodes and directory nodes before dma nodes, etc. + # + l1_cntrl_nodes = [] + l2_cntrl_nodes = [] + dir_cntrl_nodes = [] + dma_cntrl_nodes = [] + + # + # Must create the individual controllers before the network to ensure the + # controller constructors are called before the network constructor + # + + for i in xrange(options.num_cpus): + # + # First create the Ruby objects associated with this cpu + # + l1i_cache = L1Cache(size = options.l1i_size, + assoc = options.l1i_assoc) + l1d_cache = L1Cache(size = options.l1d_size, + assoc = options.l1d_assoc) + + cpu_seq = RubySequencer(icache = l1i_cache, + dcache = l1d_cache, + physMemPort = phys_mem.port, + physmem = phys_mem) + + if piobus != None: + cpu_seq.pio_port = piobus.port + + l1_cntrl = L1Cache_Controller(version = i, + sequencer = cpu_seq, + L1IcacheMemory = l1i_cache, + L1DcacheMemory = l1d_cache, + l2_select_num_bits = \ + math.log(options.num_l2caches, 2)) + # + # Add controllers and sequencers to the appropriate lists + # + cpu_sequencers.append(cpu_seq) + l1_cntrl_nodes.append(l1_cntrl) + + for i in xrange(options.num_l2caches): + # + # First create the Ruby objects associated with this cpu + # + l2_cache = L2Cache(size = options.l2_size, + assoc = options.l2_assoc) + + l2_cntrl = L2Cache_Controller(version = i, + L2cacheMemory = l2_cache) + + l2_cntrl_nodes.append(l2_cntrl) + + phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1 + mem_module_size = phys_mem_size / options.num_dirs + + for i in xrange(options.num_dirs): + # + # Create the Ruby objects associated with the directory controller + # + + mem_cntrl = RubyMemoryControl(version = i) + + dir_size = MemorySize('0B') + dir_size.value = mem_module_size + + dir_cntrl = Directory_Controller(version = i, + directory = \ + RubyDirectoryMemory(version = i, + size = dir_size), + memBuffer = mem_cntrl) + + dir_cntrl_nodes.append(dir_cntrl) + + for i, dma_device in enumerate(dma_devices): + # + # Create the Ruby objects associated with the dma controller + # + dma_seq = DMASequencer(version = i, + physMemPort = phys_mem.port, + physmem = phys_mem) + + dma_cntrl = DMA_Controller(version = i, + dma_sequencer = dma_seq) + + dma_cntrl.dma_sequencer.port = dma_device.dma + dma_cntrl_nodes.append(dma_cntrl) + + all_cntrls = l1_cntrl_nodes + \ + l2_cntrl_nodes + \ + dir_cntrl_nodes + \ + dma_cntrl_nodes + + return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py index 2b804e4bd..e86bfea1a 100644 --- a/configs/ruby/Ruby.py +++ b/configs/ruby/Ruby.py @@ -33,6 +33,7 @@ from m5.defines import buildEnv from m5.util import addToPath import MOESI_hammer +import MOESI_CMP_directory import MI_example import MOESI_CMP_token @@ -46,6 +47,12 @@ def create_system(options, physmem, piobus = None, dma_devices = []): physmem, \ piobus, \ dma_devices) + elif protocol == "MOESI_CMP_directory": + (cpu_sequencers, dir_cntrls, all_cntrls) = \ + MOESI_CMP_directory.create_system(options, \ + physmem, \ + piobus, \ + dma_devices) elif protocol == "MI_example": (cpu_sequencers, dir_cntrls, all_cntrls) = \ MI_example.create_system(options, \ diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index f6b1d4f38..3f9980d67 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -33,9 +33,11 @@ */ machine(L1Cache, "Directory protocol") - : int request_latency, - int l2_select_low_bit, - int l2_select_num_bits + : Sequencer * sequencer, + CacheMemory * L1IcacheMemory, + CacheMemory * L1DcacheMemory, + int l2_select_num_bits, + int request_latency = 2 { // NODE L1 CACHE @@ -127,16 +129,6 @@ machine(L1Cache, "Directory protocol") int NumPendingMsgs, default="0", desc="Number of acks/data messages that this processor is waiting for"; } - external_type(CacheMemory) { - bool cacheAvail(Address); - Address cacheProbe(Address); - void allocate(Address, Entry); - void deallocate(Address); - Entry lookup(Address); - void changePermission(Address, AccessPermission); - bool isTagPresent(Address); - } - external_type(TBETable) { TBE lookup(Address); void allocate(Address); @@ -146,18 +138,16 @@ machine(L1Cache, "Directory protocol") MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true"; - Sequencer sequencer, factory='RubySystem::getSequencer(m_cfg["sequencer"])'; TBETable TBEs, template_hack=""; - CacheMemory L1IcacheMemory, factory='RubySystem::getCache(m_cfg["icache"])'; - CacheMemory L1DcacheMemory, factory='RubySystem::getCache(m_cfg["dcache"])'; TimerTable useTimerTable; + int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; Entry getCacheEntry(Address addr), return_by_ref="yes" { if (L1DcacheMemory.isTagPresent(addr)) { - return L1DcacheMemory[addr]; + return static_cast(Entry, L1DcacheMemory[addr]); } else { - return L1IcacheMemory[addr]; + return static_cast(Entry, L1IcacheMemory[addr]); } } diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm index 9ee909199..dff1dab27 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm @@ -33,8 +33,9 @@ */ machine(L2Cache, "Token protocol") -: int response_latency, - int request_latency +: CacheMemory * L2cacheMemory, + int response_latency = 2, + int request_latency = 2 { // L2 BANK QUEUES @@ -209,17 +210,6 @@ machine(L2Cache, "Token protocol") bool isPresent(Address); } - external_type(CacheMemory) { - bool cacheAvail(Address); - Address cacheProbe(Address); - void allocate(Address, Entry); - void deallocate(Address); - Entry lookup(Address); - void changePermission(Address, AccessPermission); - bool isTagPresent(Address); - void setMRU(Address); - } - external_type(PerfectCacheMemory) { void allocate(Address); void deallocate(Address); @@ -229,15 +219,14 @@ machine(L2Cache, "Token protocol") TBETable L2_TBEs, template_hack=""; - CacheMemory L2cacheMemory, factory='RubySystem::getCache(m_cfg["cache"])'; PerfectCacheMemory localDirectory, template_hack=""; Entry getL2CacheEntry(Address addr), return_by_ref="yes" { if (L2cacheMemory.isTagPresent(addr)) { - return L2cacheMemory[addr]; + return static_cast(Entry, L2cacheMemory[addr]); } else { - return L2cacheMemory[addr]; + return static_cast(Entry, L2cacheMemory[addr]); } } @@ -258,11 +247,11 @@ machine(L2Cache, "Token protocol") bool isOnlySharer(Address addr, MachineID shar_id) { if (isCacheTagPresent(addr)) { assert (localDirectory.isTagPresent(addr) == false); - if (L2cacheMemory[addr].Sharers.count() > 1) { + if (getL2CacheEntry(addr).Sharers.count() > 1) { return false; } - else if (L2cacheMemory[addr].Sharers.count() == 1) { - if (L2cacheMemory[addr].Sharers.isElement(shar_id)) { + else if (getL2CacheEntry(addr).Sharers.count() == 1) { + if (getL2CacheEntry(addr).Sharers.isElement(shar_id)) { return true; } else { @@ -299,24 +288,24 @@ machine(L2Cache, "Token protocol") void copyCacheStateToDir(Address addr) { assert(localDirectory.isTagPresent(addr) == false); localDirectory.allocate(addr); - localDirectory[addr].DirState := L2cacheMemory[addr].CacheState; - localDirectory[addr].Sharers := L2cacheMemory[addr].Sharers; - localDirectory[addr].Owner := L2cacheMemory[addr].Owner; - localDirectory[addr].OwnerValid := L2cacheMemory[addr].OwnerValid; + localDirectory[addr].DirState := getL2CacheEntry(addr).CacheState; + localDirectory[addr].Sharers := getL2CacheEntry(addr).Sharers; + localDirectory[addr].Owner := getL2CacheEntry(addr).Owner; + localDirectory[addr].OwnerValid := getL2CacheEntry(addr).OwnerValid; } void copyDirToCache(Address addr) { - L2cacheMemory[addr].Sharers := localDirectory[addr].Sharers; - L2cacheMemory[addr].Owner := localDirectory[addr].Owner; - L2cacheMemory[addr].OwnerValid := localDirectory[addr].OwnerValid; + getL2CacheEntry(addr).Sharers := localDirectory[addr].Sharers; + getL2CacheEntry(addr).Owner := localDirectory[addr].Owner; + getL2CacheEntry(addr).OwnerValid := localDirectory[addr].OwnerValid; } void recordLocalSharerInDir(Address addr, MachineID shar_id) { if (isCacheTagPresent(addr)) { assert (localDirectory.isTagPresent(addr) == false); - L2cacheMemory[addr].Sharers.add(shar_id); + getL2CacheEntry(addr).Sharers.add(shar_id); } else { if (localDirectory.isTagPresent(addr) == false) { @@ -332,9 +321,9 @@ machine(L2Cache, "Token protocol") if (isCacheTagPresent(addr)) { assert (localDirectory.isTagPresent(addr) == false); - L2cacheMemory[addr].Sharers.clear(); - L2cacheMemory[addr].OwnerValid := true; - L2cacheMemory[addr].Owner := exc_id; + getL2CacheEntry(addr).Sharers.clear(); + getL2CacheEntry(addr).OwnerValid := true; + getL2CacheEntry(addr).Owner := exc_id; } else { if (localDirectory.isTagPresent(addr) == false) { @@ -350,8 +339,8 @@ machine(L2Cache, "Token protocol") void removeAllLocalSharersFromDir(Address addr) { if (isCacheTagPresent(addr)) { assert (localDirectory.isTagPresent(addr) == false); - L2cacheMemory[addr].Sharers.clear(); - L2cacheMemory[addr].OwnerValid := false; + getL2CacheEntry(addr).Sharers.clear(); + getL2CacheEntry(addr).OwnerValid := false; } else { localDirectory[addr].Sharers.clear(); @@ -362,7 +351,7 @@ machine(L2Cache, "Token protocol") void removeSharerFromDir(Address addr, MachineID sender) { if (isCacheTagPresent(addr)) { assert (localDirectory.isTagPresent(addr) == false); - L2cacheMemory[addr].Sharers.remove(sender); + getL2CacheEntry(addr).Sharers.remove(sender); } else { localDirectory[addr].Sharers.remove(sender); @@ -372,7 +361,7 @@ machine(L2Cache, "Token protocol") void removeOwnerFromDir(Address addr, MachineID sender) { if (isCacheTagPresent(addr)) { assert (localDirectory.isTagPresent(addr) == false); - L2cacheMemory[addr].OwnerValid := false; + getL2CacheEntry(addr).OwnerValid := false; } else { localDirectory[addr].OwnerValid := false; @@ -382,7 +371,7 @@ machine(L2Cache, "Token protocol") bool isLocalSharer(Address addr, MachineID shar_id) { if (isCacheTagPresent(addr)) { assert (localDirectory.isTagPresent(addr) == false); - return L2cacheMemory[addr].Sharers.isElement(shar_id); + return getL2CacheEntry(addr).Sharers.isElement(shar_id); } else { return localDirectory[addr].Sharers.isElement(shar_id); @@ -393,7 +382,7 @@ machine(L2Cache, "Token protocol") NetDest getLocalSharers(Address addr) { if (isCacheTagPresent(addr)) { assert (localDirectory.isTagPresent(addr) == false); - return L2cacheMemory[addr].Sharers; + return getL2CacheEntry(addr).Sharers; } else { return localDirectory[addr].Sharers; @@ -404,7 +393,7 @@ machine(L2Cache, "Token protocol") MachineID getLocalOwner(Address addr) { if (isCacheTagPresent(addr)) { assert (localDirectory.isTagPresent(addr) == false); - return L2cacheMemory[addr].Owner; + return getL2CacheEntry(addr).Owner; } else { return localDirectory[addr].Owner; @@ -416,7 +405,7 @@ machine(L2Cache, "Token protocol") int countLocalSharers(Address addr) { if (isCacheTagPresent(addr)) { assert (localDirectory.isTagPresent(addr) == false); - return L2cacheMemory[addr].Sharers.count(); + return getL2CacheEntry(addr).Sharers.count(); } else { return localDirectory[addr].Sharers.count(); @@ -426,7 +415,7 @@ machine(L2Cache, "Token protocol") bool isLocalOwnerValid(Address addr) { if (isCacheTagPresent(addr)) { assert (localDirectory.isTagPresent(addr) == false); - return L2cacheMemory[addr].OwnerValid; + return getL2CacheEntry(addr).OwnerValid; } else { return localDirectory[addr].OwnerValid; @@ -436,11 +425,11 @@ machine(L2Cache, "Token protocol") int countLocalSharersExceptRequestor(Address addr, MachineID requestor) { if (isCacheTagPresent(addr)) { assert (localDirectory.isTagPresent(addr) == false); - if (L2cacheMemory[addr].Sharers.isElement(requestor)) { - return ( L2cacheMemory[addr].Sharers.count() - 1 ); + if (getL2CacheEntry(addr).Sharers.isElement(requestor)) { + return ( getL2CacheEntry(addr).Sharers.count() - 1 ); } else { - return L2cacheMemory[addr].Sharers.count(); + return getL2CacheEntry(addr).Sharers.count(); } } else { diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm index 9e6cc918d..74a785808 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dir.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm @@ -32,7 +32,9 @@ */ machine(Directory, "Directory protocol") -: int directory_latency +: DirectoryMemory * directory, + MemoryControl * memBuffer, + int directory_latency = 6 { // ** IN QUEUES ** @@ -92,7 +94,7 @@ machine(Directory, "Directory protocol") // TYPES // DirectoryEntry - structure(Entry, desc="...") { + structure(Entry, desc="...", interface='AbstractEntry') { State DirectoryState, desc="Directory state"; DataBlock DataBlk, desc="data for the block"; NetDest Sharers, desc="Sharers for this block"; @@ -107,11 +109,6 @@ machine(Directory, "Directory protocol") MachineID Requestor, desc="original requestor"; } - external_type(DirectoryMemory) { - Entry lookup(Address); - bool isPresent(Address); - } - external_type(TBETable) { TBE lookup(Address); void allocate(Address); @@ -119,55 +116,50 @@ machine(Directory, "Directory protocol") bool isPresent(Address); } - // to simulate detailed DRAM - external_type(MemoryControl, inport="yes", outport="yes") { - - } - - // ** OBJECTS ** - - DirectoryMemory directory, factory='RubySystem::getDirectory(m_cfg["directory"])'; - MemoryControl memBuffer, factory='RubySystem::getMemoryControl(m_cfg["memory_control"])'; TBETable TBEs, template_hack=""; + Entry getDirectoryEntry(Address addr), return_by_ref="yes" { + return static_cast(Entry, directory[addr]); + } + State getState(Address addr) { - return directory[addr].DirectoryState; + return getDirectoryEntry(addr).DirectoryState; } void setState(Address addr, State state) { if (directory.isPresent(addr)) { if (state == State:I) { - assert(directory[addr].Owner.count() == 0); - assert(directory[addr].Sharers.count() == 0); + assert(getDirectoryEntry(addr).Owner.count() == 0); + assert(getDirectoryEntry(addr).Sharers.count() == 0); } if (state == State:S) { - assert(directory[addr].Owner.count() == 0); + assert(getDirectoryEntry(addr).Owner.count() == 0); } if (state == State:O) { - assert(directory[addr].Owner.count() == 1); - assert(directory[addr].Sharers.isSuperset(directory[addr].Owner) == false); + assert(getDirectoryEntry(addr).Owner.count() == 1); + assert(getDirectoryEntry(addr).Sharers.isSuperset(getDirectoryEntry(addr).Owner) == false); } if (state == State:M) { - assert(directory[addr].Owner.count() == 1); - assert(directory[addr].Sharers.count() == 0); + assert(getDirectoryEntry(addr).Owner.count() == 1); + assert(getDirectoryEntry(addr).Sharers.count() == 0); } if ((state != State:SS) && (state != State:OO)) { - assert(directory[addr].WaitingUnblocks == 0); + assert(getDirectoryEntry(addr).WaitingUnblocks == 0); } - if ( (directory[addr].DirectoryState != State:I) && (state == State:I) ) { - directory[addr].DirectoryState := state; + if ( (getDirectoryEntry(addr).DirectoryState != State:I) && (state == State:I) ) { + getDirectoryEntry(addr).DirectoryState := state; // disable coherence checker // sequencer.checkCoherence(addr); } else { - directory[addr].DirectoryState := state; + getDirectoryEntry(addr).DirectoryState := state; } } } @@ -175,7 +167,7 @@ machine(Directory, "Directory protocol") // if no sharers, then directory can be considered both a sharer and exclusive w.r.t. coherence checking bool isBlockShared(Address addr) { if (directory.isPresent(addr)) { - if (directory[addr].DirectoryState == State:I) { + if (getDirectoryEntry(addr).DirectoryState == State:I) { return true; } } @@ -184,7 +176,7 @@ machine(Directory, "Directory protocol") bool isBlockExclusive(Address addr) { if (directory.isPresent(addr)) { - if (directory[addr].DirectoryState == State:I) { + if (getDirectoryEntry(addr).DirectoryState == State:I) { return true; } } @@ -211,7 +203,7 @@ machine(Directory, "Directory protocol") if (unblockNetwork_in.isReady()) { peek(unblockNetwork_in, ResponseMsg) { if (in_msg.Type == CoherenceResponseType:UNBLOCK) { - if (directory[in_msg.Address].WaitingUnblocks == 1) { + if (getDirectoryEntry(in_msg.Address).WaitingUnblocks == 1) { trigger(Event:Last_Unblock, in_msg.Address); } else { trigger(Event:Unblock, in_msg.Address); @@ -298,16 +290,16 @@ machine(Directory, "Directory protocol") } action(c_clearOwner, "c", desc="Clear the owner field") { - directory[address].Owner.clear(); + getDirectoryEntry(address).Owner.clear(); } action(c_moveOwnerToSharer, "cc", desc="Move owner to sharers") { - directory[address].Sharers.addNetDest(directory[address].Owner); - directory[address].Owner.clear(); + getDirectoryEntry(address).Sharers.addNetDest(getDirectoryEntry(address).Owner); + getDirectoryEntry(address).Owner.clear(); } action(cc_clearSharers, "\c", desc="Clear the sharers field") { - directory[address].Sharers.clear(); + getDirectoryEntry(address).Sharers.clear(); } action(d_sendDataMsg, "d", desc="Send data to requestor") { @@ -317,7 +309,7 @@ machine(Directory, "Directory protocol") out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:Directory; out_msg.Destination.add(in_msg.OriginalRequestorMachId); - //out_msg.DataBlk := directory[in_msg.Address].DataBlk; + //out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk; out_msg.DataBlk := in_msg.DataBlk; out_msg.Dirty := false; // By definition, the block is now clean out_msg.Acks := in_msg.Acks; @@ -338,7 +330,7 @@ machine(Directory, "Directory protocol") out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:Directory; out_msg.Destination.add(in_msg.Requestor); - out_msg.DataBlk := directory[in_msg.Address].DataBlk; + out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk; out_msg.Dirty := false; // By definition, the block is now clean out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.MessageSize := MessageSizeType:Response_Data; @@ -350,8 +342,8 @@ machine(Directory, "Directory protocol") action(e_ownerIsUnblocker, "e", desc="The owner is now the unblocker") { peek(unblockNetwork_in, ResponseMsg) { - directory[address].Owner.clear(); - directory[address].Owner.add(in_msg.Sender); + getDirectoryEntry(address).Owner.clear(); + getDirectoryEntry(address).Owner.add(in_msg.Sender); } } @@ -361,9 +353,9 @@ machine(Directory, "Directory protocol") out_msg.Address := address; out_msg.Type := in_msg.Type; out_msg.Requestor := in_msg.Requestor; - out_msg.Destination.addNetDest(directory[in_msg.Address].Owner); - out_msg.Acks := directory[address].Sharers.count(); - if (directory[address].Sharers.isElement(in_msg.Requestor)) { + out_msg.Destination.addNetDest(getDirectoryEntry(in_msg.Address).Owner); + out_msg.Acks := getDirectoryEntry(address).Sharers.count(); + if (getDirectoryEntry(address).Sharers.isElement(in_msg.Requestor)) { out_msg.Acks := out_msg.Acks - 1; } out_msg.MessageSize := MessageSizeType:Forwarded_Control; @@ -377,9 +369,9 @@ machine(Directory, "Directory protocol") out_msg.Address := address; out_msg.Type := in_msg.Type; out_msg.Requestor := machineID; - out_msg.Destination.addNetDest(directory[in_msg.Address].Owner); - out_msg.Acks := directory[address].Sharers.count(); - if (directory[address].Sharers.isElement(in_msg.Requestor)) { + out_msg.Destination.addNetDest(getDirectoryEntry(in_msg.Address).Owner); + out_msg.Acks := getDirectoryEntry(address).Sharers.count(); + if (getDirectoryEntry(address).Sharers.isElement(in_msg.Requestor)) { out_msg.Acks := out_msg.Acks - 1; } out_msg.MessageSize := MessageSizeType:Forwarded_Control; @@ -389,14 +381,14 @@ machine(Directory, "Directory protocol") action(g_sendInvalidations, "g", desc="Send invalidations to sharers, not including the requester") { peek(requestQueue_in, RequestMsg) { - if ((directory[in_msg.Address].Sharers.count() > 1) || - ((directory[in_msg.Address].Sharers.count() > 0) && (directory[in_msg.Address].Sharers.isElement(in_msg.Requestor) == false))) { + if ((getDirectoryEntry(in_msg.Address).Sharers.count() > 1) || + ((getDirectoryEntry(in_msg.Address).Sharers.count() > 0) && (getDirectoryEntry(in_msg.Address).Sharers.isElement(in_msg.Requestor) == false))) { enqueue(forwardNetwork_out, RequestMsg, latency=directory_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:INV; out_msg.Requestor := in_msg.Requestor; - // out_msg.Destination := directory[in_msg.Address].Sharers; - out_msg.Destination.addNetDest(directory[in_msg.Address].Sharers); + // out_msg.Destination := getDirectoryEntry(in_msg.Address).Sharers; + out_msg.Destination.addNetDest(getDirectoryEntry(in_msg.Address).Sharers); out_msg.Destination.remove(in_msg.Requestor); out_msg.MessageSize := MessageSizeType:Invalidate_Control; } @@ -416,7 +408,7 @@ machine(Directory, "Directory protocol") peek(unblockNetwork_in, ResponseMsg) { assert(in_msg.Dirty); assert(in_msg.MessageSize == MessageSizeType:Writeback_Data); - directory[in_msg.Address].DataBlk := in_msg.DataBlk; + getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk; DEBUG_EXPR(in_msg.Address); DEBUG_EXPR(in_msg.DataBlk); } @@ -424,7 +416,7 @@ machine(Directory, "Directory protocol") action(p_writeFwdDataToMemory, "p", desc="Write Response data to memory") { peek(unblockNetwork_in, ResponseMsg) { - directory[in_msg.Address].DataBlk := in_msg.DataBlk; + getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk; DEBUG_EXPR(in_msg.Address); DEBUG_EXPR(in_msg.DataBlk); } @@ -439,23 +431,23 @@ machine(Directory, "Directory protocol") // implementation. We include the data in the "dataless" // message so we can assert the clean data matches the datablock // in memory - assert(directory[in_msg.Address].DataBlk == in_msg.DataBlk); + assert(getDirectoryEntry(in_msg.Address).DataBlk == in_msg.DataBlk); } } action(m_addUnlockerToSharers, "m", desc="Add the unlocker to the sharer list") { peek(unblockNetwork_in, ResponseMsg) { - directory[address].Sharers.add(in_msg.Sender); + getDirectoryEntry(address).Sharers.add(in_msg.Sender); } } action(n_incrementOutstanding, "n", desc="Increment outstanding requests") { - directory[address].WaitingUnblocks := directory[address].WaitingUnblocks + 1; + getDirectoryEntry(address).WaitingUnblocks := getDirectoryEntry(address).WaitingUnblocks + 1; } action(o_decrementOutstanding, "o", desc="Decrement outstanding requests") { - directory[address].WaitingUnblocks := directory[address].WaitingUnblocks - 1; - assert(directory[address].WaitingUnblocks >= 0); + getDirectoryEntry(address).WaitingUnblocks := getDirectoryEntry(address).WaitingUnblocks - 1; + assert(getDirectoryEntry(address).WaitingUnblocks >= 0); } action(q_popMemQueue, "q", desc="Pop off-chip request queue") { @@ -469,13 +461,13 @@ machine(Directory, "Directory protocol") out_msg.Type := MemoryRequestType:MEMORY_READ; out_msg.Sender := machineID; out_msg.OriginalRequestorMachId := in_msg.Requestor; - out_msg.DataBlk := directory[in_msg.Address].DataBlk; + out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk; out_msg.MessageSize := in_msg.MessageSize; //out_msg.Prefetch := false; // These are not used by memory but are passed back here with the read data: - out_msg.ReadX := (in_msg.Type == CoherenceRequestType:GETS && directory[address].Sharers.count() == 0); - out_msg.Acks := directory[address].Sharers.count(); - if (directory[address].Sharers.isElement(in_msg.Requestor)) { + out_msg.ReadX := (in_msg.Type == CoherenceRequestType:GETS && getDirectoryEntry(address).Sharers.count() == 0); + out_msg.Acks := getDirectoryEntry(address).Sharers.count(); + if (getDirectoryEntry(address).Sharers.isElement(in_msg.Requestor)) { out_msg.Acks := out_msg.Acks - 1; } DEBUG_EXPR(out_msg); @@ -497,7 +489,7 @@ machine(Directory, "Directory protocol") //out_msg.Prefetch := false; // Not used: out_msg.ReadX := false; - out_msg.Acks := directory[address].Sharers.count(); // for dma requests + out_msg.Acks := getDirectoryEntry(address).Sharers.count(); // for dma requests DEBUG_EXPR(out_msg); } } @@ -515,7 +507,7 @@ machine(Directory, "Directory protocol") //out_msg.Prefetch := false; // Not used: out_msg.ReadX := false; - out_msg.Acks := directory[address].Sharers.count(); // for dma requests + out_msg.Acks := getDirectoryEntry(address).Sharers.count(); // for dma requests DEBUG_EXPR(out_msg); } } @@ -538,7 +530,7 @@ machine(Directory, "Directory protocol") out_msg.SenderMachine := MachineType:Directory; out_msg.Destination.add(in_msg.Requestor); out_msg.DataBlk := in_msg.DataBlk; - out_msg.Acks := directory[address].Sharers.count(); // for dma requests + out_msg.Acks := getDirectoryEntry(address).Sharers.count(); // for dma requests out_msg.Type := CoherenceResponseType:DMA_ACK; out_msg.MessageSize := MessageSizeType:Writeback_Control; } @@ -555,7 +547,7 @@ machine(Directory, "Directory protocol") out_msg.Destination.add(TBEs[address].Requestor); } out_msg.DataBlk := in_msg.DataBlk; - out_msg.Acks := directory[address].Sharers.count(); // for dma requests + out_msg.Acks := getDirectoryEntry(address).Sharers.count(); // for dma requests out_msg.Type := CoherenceResponseType:DMA_ACK; out_msg.MessageSize := MessageSizeType:Writeback_Control; } @@ -564,12 +556,12 @@ machine(Directory, "Directory protocol") action(l_writeDMADataToMemory, "\l", desc="Write data from a DMA_WRITE to memory") { peek(requestQueue_in, RequestMsg) { - directory[address].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len); + getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len); } } action(l_writeDMADataToMemoryFromTBE, "\ll", desc="Write data from a DMA_WRITE to memory") { - directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, + getDirectoryEntry(address).DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len); } diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm index 6105778bd..673e0c4cb 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -1,7 +1,8 @@ machine(DMA, "DMA Controller") -: int request_latency, - int response_latency +: DMASequencer * dma_sequencer, + int request_latency = 14, + int response_latency = 14 { MessageBuffer goo1, network="From", virtual_network="0", ordered="false"; @@ -47,7 +48,6 @@ machine(DMA, "DMA Controller") MessageBuffer mandatoryQueue, ordered="false"; MessageBuffer triggerQueue, ordered="true"; - DMASequencer dma_sequencer, factory='RubySystem::getDMASequencer(m_cfg["dma_sequencer"])'; TBETable TBEs, template_hack=""; State cur_state;