ruby: Reordered protocol buffers

Reordered vnet priorities to agree with PerfectSwitch for protocols MI_example,
MOESI_CMP_token, and MOESI_hammer
This commit is contained in:
Brad Beckmann 2010-03-21 21:22:21 -07:00
parent 4f044605e8
commit 61f1d9a3d7
10 changed files with 50 additions and 50 deletions

View file

@ -7,11 +7,11 @@ machine(L1Cache, "MI Example L1 Cache")
{
// NETWORK BUFFERS
MessageBuffer requestFromCache, network="To", virtual_network="0", ordered="true";
MessageBuffer responseFromCache, network="To", virtual_network="1", ordered="true";
MessageBuffer requestFromCache, network="To", virtual_network="2", ordered="true";
MessageBuffer responseFromCache, network="To", virtual_network="4", ordered="true";
MessageBuffer forwardToCache, network="From", virtual_network="2", ordered="true";
MessageBuffer responseToCache, network="From", virtual_network="1", ordered="true";
MessageBuffer forwardToCache, network="From", virtual_network="3", ordered="true";
MessageBuffer responseToCache, network="From", virtual_network="4", ordered="true";
// STATES
enumeration(State, desc="Cache states") {

View file

@ -5,12 +5,12 @@ machine(Directory, "Directory protocol")
int directory_latency = 12
{
MessageBuffer forwardFromDir, network="To", virtual_network="2", ordered="false";
MessageBuffer responseFromDir, network="To", virtual_network="1", ordered="false";
MessageBuffer dmaRequestFromDir, network="To", virtual_network="4", ordered="true";
MessageBuffer forwardFromDir, network="To", virtual_network="3", ordered="false";
MessageBuffer responseFromDir, network="To", virtual_network="4", ordered="false";
MessageBuffer dmaResponseFromDir, network="To", virtual_network="1", ordered="true";
MessageBuffer requestToDir, network="From", virtual_network="0", ordered="true";
MessageBuffer dmaRequestToDir, network="From", virtual_network="5", ordered="true";
MessageBuffer requestToDir, network="From", virtual_network="2", ordered="true";
MessageBuffer dmaRequestToDir, network="From", virtual_network="0", ordered="true";
// STATES
enumeration(State, desc="Directory states", default="Directory_State_I") {
@ -117,7 +117,7 @@ machine(Directory, "Directory protocol")
out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
out_port(responseNetwork_out, ResponseMsg, responseFromDir);
out_port(requestQueue_out, ResponseMsg, requestToDir); // For recycling requests
out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaRequestFromDir);
out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaResponseFromDir);
//added by SS
out_port(memQueue_out, MemoryMsg, memBuffer);

View file

@ -4,8 +4,8 @@ machine(DMA, "DMA Controller")
int request_latency = 6
{
MessageBuffer responseFromDir, network="From", virtual_network="4", ordered="true", no_vector="true";
MessageBuffer reqToDirectory, network="To", virtual_network="5", ordered="false", no_vector="true";
MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", no_vector="true";
MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", no_vector="true";
enumeration(State, desc="DMA states", default="DMA_State_READY") {
READY, desc="Ready to accept a new request";

View file

@ -48,18 +48,18 @@ machine(L1Cache, "Token protocol")
// From this node's L1 cache TO the network
// a local L1 -> this L2 bank
MessageBuffer responseFromL1Cache, network="To", virtual_network="1", ordered="false";
MessageBuffer persistentFromL1Cache, network="To", virtual_network="2", ordered="true";
MessageBuffer responseFromL1Cache, network="To", virtual_network="4", ordered="false";
MessageBuffer persistentFromL1Cache, network="To", virtual_network="3", ordered="true";
// a local L1 -> this L2 bank, currently ordered with directory forwarded requests
MessageBuffer requestFromL1Cache, network="To", virtual_network="4", ordered="false";
MessageBuffer requestFromL1Cache, network="To", virtual_network="1", ordered="false";
// To this node's L1 cache FROM the network
// a L2 bank -> this L1
MessageBuffer responseToL1Cache, network="From", virtual_network="1", ordered="false";
MessageBuffer persistentToL1Cache, network="From", virtual_network="2", ordered="true";
MessageBuffer responseToL1Cache, network="From", virtual_network="4", ordered="false";
MessageBuffer persistentToL1Cache, network="From", virtual_network="3", ordered="true";
// a L2 bank -> this L1
MessageBuffer requestToL1Cache, network="From", virtual_network="4", ordered="false";
MessageBuffer requestToL1Cache, network="From", virtual_network="1", ordered="false";
// STATES
enumeration(State, desc="Cache states", default="L1Cache_State_I") {

View file

@ -44,22 +44,22 @@ machine(L2Cache, "Token protocol")
// From local bank of L2 cache TO the network
// this L2 bank -> a local L1 || mod-directory
MessageBuffer responseFromL2Cache, network="To", virtual_network="1", ordered="false";
MessageBuffer responseFromL2Cache, network="To", virtual_network="4", ordered="false";
// this L2 bank -> mod-directory
MessageBuffer GlobalRequestFromL2Cache, network="To", virtual_network="3", ordered="false";
MessageBuffer GlobalRequestFromL2Cache, network="To", virtual_network="2", ordered="false";
// this L2 bank -> a local L1
MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="4", ordered="false";
MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="1", ordered="false";
// FROM the network to this local bank of L2 cache
// a local L1 || mod-directory -> this L2 bank
MessageBuffer responseToL2Cache, network="From", virtual_network="1", ordered="false";
MessageBuffer persistentToL2Cache, network="From", virtual_network="2", ordered="true";
MessageBuffer responseToL2Cache, network="From", virtual_network="4", ordered="false";
MessageBuffer persistentToL2Cache, network="From", virtual_network="3", ordered="true";
// mod-directory -> this L2 bank
MessageBuffer GlobalRequestToL2Cache, network="From", virtual_network="3", ordered="false";
MessageBuffer GlobalRequestToL2Cache, network="From", virtual_network="2", ordered="false";
// a local L1 -> this L2 bank
MessageBuffer L1RequestToL2Cache, network="From", virtual_network="4", ordered="false";
MessageBuffer L1RequestToL2Cache, network="From", virtual_network="1", ordered="false";
// STATES
enumeration(State, desc="L2 Cache states", default="L2Cache_State_I") {

View file

@ -41,15 +41,15 @@ machine(Directory, "Token protocol")
int fixed_timeout_latency = 300
{
MessageBuffer dmaResponseFromDir, network="To", virtual_network="0", ordered="true";
MessageBuffer responseFromDir, network="To", virtual_network="1", ordered="false";
MessageBuffer persistentFromDir, network="To", virtual_network="2", ordered="true";
MessageBuffer requestFromDir, network="To", virtual_network="4", ordered="false";
MessageBuffer dmaResponseFromDir, network="To", virtual_network="5", ordered="true";
MessageBuffer responseFromDir, network="To", virtual_network="4", ordered="false";
MessageBuffer persistentFromDir, network="To", virtual_network="3", ordered="true";
MessageBuffer requestFromDir, network="To", virtual_network="1", ordered="false";
MessageBuffer responseToDir, network="From", virtual_network="1", ordered="false";
MessageBuffer persistentToDir, network="From", virtual_network="2", ordered="true";
MessageBuffer requestToDir, network="From", virtual_network="3", ordered="false";
MessageBuffer dmaRequestToDir, network="From", virtual_network="5", ordered="true";
MessageBuffer responseToDir, network="From", virtual_network="4", ordered="false";
MessageBuffer persistentToDir, network="From", virtual_network="3", ordered="true";
MessageBuffer requestToDir, network="From", virtual_network="2", ordered="false";
MessageBuffer dmaRequestToDir, network="From", virtual_network="0", ordered="true";
// STATES
enumeration(State, desc="Directory states", default="Directory_State_O") {

View file

@ -32,8 +32,8 @@ machine(DMA, "DMA Controller")
int request_latency = 6
{
MessageBuffer responseFromDir, network="From", virtual_network="0", ordered="true", no_vector="true";
MessageBuffer reqToDirectory, network="To", virtual_network="5", ordered="false", no_vector="true";
MessageBuffer responseFromDir, network="From", virtual_network="5", ordered="true", no_vector="true";
MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", no_vector="true";
enumeration(State, desc="DMA states", default="DMA_State_READY") {
READY, desc="Ready to accept a new request";

View file

@ -43,12 +43,12 @@ machine(L1Cache, "AMD Hammer-like protocol")
{
// NETWORK BUFFERS
MessageBuffer requestFromCache, network="To", virtual_network="3", ordered="false";
MessageBuffer responseFromCache, network="To", virtual_network="1", ordered="false";
MessageBuffer unblockFromCache, network="To", virtual_network="0", ordered="false";
MessageBuffer requestFromCache, network="To", virtual_network="2", ordered="false";
MessageBuffer responseFromCache, network="To", virtual_network="4", ordered="false";
MessageBuffer unblockFromCache, network="To", virtual_network="5", ordered="false";
MessageBuffer forwardToCache, network="From", virtual_network="2", ordered="false";
MessageBuffer responseToCache, network="From", virtual_network="1", ordered="false";
MessageBuffer forwardToCache, network="From", virtual_network="3", ordered="false";
MessageBuffer responseToCache, network="From", virtual_network="4", ordered="false";
// STATES

View file

@ -39,19 +39,19 @@ machine(Directory, "AMD Hammer-like protocol")
int memory_controller_latency = 12
{
MessageBuffer forwardFromDir, network="To", virtual_network="2", ordered="false";
MessageBuffer responseFromDir, network="To", virtual_network="1", ordered="false";
MessageBuffer forwardFromDir, network="To", virtual_network="3", ordered="false";
MessageBuffer responseFromDir, network="To", virtual_network="4", ordered="false";
//
// For a finite buffered network, note that the DMA response network only
// works at this relatively higher numbered (lower priority) virtual network
// works at this relatively lower numbered (lower priority) virtual network
// because the trigger queue decouples cache responses from DMA responses.
//
MessageBuffer dmaResponseFromDir, network="To", virtual_network="4", ordered="true";
MessageBuffer dmaResponseFromDir, network="To", virtual_network="1", ordered="true";
MessageBuffer unblockToDir, network="From", virtual_network="0", ordered="false";
MessageBuffer responseToDir, network="From", virtual_network="1", ordered="false";
MessageBuffer requestToDir, network="From", virtual_network="3", ordered="false";
MessageBuffer dmaRequestToDir, network="From", virtual_network="5", ordered="true";
MessageBuffer unblockToDir, network="From", virtual_network="5", ordered="false";
MessageBuffer responseToDir, network="From", virtual_network="4", ordered="false";
MessageBuffer requestToDir, network="From", virtual_network="2", ordered="false";
MessageBuffer dmaRequestToDir, network="From", virtual_network="0", ordered="true";
// STATES
enumeration(State, desc="Directory states", default="Directory_State_E") {

View file

@ -32,8 +32,8 @@ machine(DMA, "DMA Controller")
int request_latency = 6
{
MessageBuffer responseFromDir, network="From", virtual_network="4", ordered="true", no_vector="true";
MessageBuffer reqToDirectory, network="To", virtual_network="5", ordered="false", no_vector="true";
MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", no_vector="true";
MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", no_vector="true";
enumeration(State, desc="DMA states", default="DMA_State_READY") {
READY, desc="Ready to accept a new request";