gem5/src
Gabe Black 3a55fc5cac X86: Implement shift right/left double microops.
This is my best guess as far as what these should do. Other existing microops
use implicit registers, mul1s and mul1u for instance, so this should be ok.
The microop that loads the implicit DoubleBits register would fall into one
of the microop slots for moving to/from special registers.
2009-08-07 10:13:20 -07:00
..
arch X86: Implement shift right/left double microops. 2009-08-07 10:13:20 -07:00
base ARM: Detect OABI binaries and complain that they're no-longer supported. 2009-07-27 00:50:55 -07:00
cpu Fix setting of INST_FETCH flag for O3 CPU. 2009-08-01 22:50:14 -07:00
dev X86: Set up the IDE device correctly, ie. with and using legacy ports. 2009-08-02 18:01:13 -07:00
doxygen Fix up doxygen. 2006-08-14 19:25:07 -04:00
kern Alpha: Pull the MiscRegFile fully into the ISA object. 2009-07-08 23:02:22 -07:00
mem merge 2009-08-05 14:23:32 -05:00
python attrdict: correct delattr 2009-07-02 16:48:22 -07:00
sim Elf: Add in some new aux vector type constants. 2009-07-27 00:52:19 -07:00
unittest includes: sort includes again 2009-05-17 14:34:52 -07:00
Doxyfile Fix up doxygen. 2006-08-14 19:25:07 -04:00
SConscript scons: Make shared library builds work again 2009-06-12 21:19:16 -07:00