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Functionality migrated to sequencer.

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This commit is contained in:
Polina Dudnik 2009-09-17 17:39:52 -05:00
parent 31a3ef03cb
commit 114d8724dd
6 changed files with 119 additions and 70 deletions
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2
src/mem/ruby/network/simple/PerfectSwitch.cc
View file

@ -184,7 +184,7 @@ void PerfectSwitch::wakeup()
assert(m_link_order.size() == m_routing_table.size());
assert(m_link_order.size() == m_out.size());
//changed by SS
if (m_network_ptr->getAdaptiveRouting()) {
if (m_network_ptr->isVNetOrdered(vnet)) {
// Don't adaptively route

4
src/mem/ruby/slicc_interface/AbstractController.hh
View file

@ -22,8 +22,8 @@ public:
virtual const string getName() const = 0; // return instance name
virtual const MachineType getMachineType() const = 0;
virtual void set_atomic(Address addr) = 0;
virtual void started_writes() = 0;
virtual void clear_atomic() = 0;
virtual void clear_atomic(Address addr) = 0;
virtual void reset_atomics() = 0;
virtual void print(ostream & out) const = 0;
virtual void printStats(ostream & out) const = 0;

77
src/mem/ruby/system/Sequencer.cc
View file

@ -62,8 +62,8 @@ void Sequencer::init(const vector<string> & argv)
m_instCache_ptr = NULL;
m_dataCache_ptr = NULL;
m_controller = NULL;
m_servicing_atomic = 200;
m_atomics_counter = 0;
m_atomic_reads = 0;
m_atomic_writes = 0;
for (size_t i=0; i<argv.size(); i+=2) {
if ( argv[i] == "controller") {
m_controller = RubySystem::getController(argv[i+1]); // args[i] = "L1Cache"
@ -265,6 +265,7 @@ void Sequencer::writeCallback(const Address& address, DataBlock& data) {
assert(m_writeRequestTable.exist(line_address(address)));
SequencerRequest* request = m_writeRequestTable.lookup(address);
removeRequest(request);
assert((request->ruby_request.type == RubyRequestType_ST) ||
@ -280,7 +281,7 @@ void Sequencer::writeCallback(const Address& address, DataBlock& data) {
m_controller->set_atomic(address);
}
else if (request->ruby_request.type == RubyRequestType_RMW_Write) {
m_controller->clear_atomic();
m_controller->clear_atomic(address);
}
hitCallback(request, data);
@ -346,16 +347,7 @@ void Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data) {
data.setData(ruby_request.data, request_address.getOffset(), ruby_request.len);
}
}
if (type == RubyRequestType_RMW_Write) {
if (m_servicing_atomic != ruby_request.proc_id) {
assert(0);
}
assert(m_atomics_counter > 0);
m_atomics_counter--;
if (m_atomics_counter == 0) {
m_servicing_atomic = 200;
}
}
m_hit_callback(srequest->id);
delete srequest;
}
@ -376,25 +368,6 @@ int Sequencer::isReady(const RubyRequest& request) {
return LIBRUBY_ALIASED_REQUEST;
}
if (request.type == RubyRequestType_RMW_Read) {
if (m_servicing_atomic == 200) {
assert(m_atomics_counter == 0);
m_servicing_atomic = request.proc_id;
}
else {
assert(m_servicing_atomic == request.proc_id);
}
m_atomics_counter++;
}
else {
if (m_servicing_atomic == request.proc_id) {
if (request.type != RubyRequestType_RMW_Write) {
m_servicing_atomic = 200;
m_atomics_counter = 0;
}
}
}
return 1;
}
@ -422,9 +395,6 @@ int64_t Sequencer::makeRequest(const RubyRequest & request)
m_dataCache_ptr->clearLocked(line_address(Address(request.paddr)));
}
}
if (request.type == RubyRequestType_RMW_Write) {
m_controller->started_writes();
}
issueRequest(request);
// TODO: issue hardware prefetches here
@ -445,18 +415,55 @@ void Sequencer::issueRequest(const RubyRequest& request) {
CacheRequestType ctype;
switch(request.type) {
case RubyRequestType_IFETCH:
if (m_atomic_reads > 0 && m_atomic_writes == 0) {
m_controller->reset_atomics();
}
else if (m_atomic_writes > 0) {
assert(m_atomic_reads > m_atomic_writes);
cerr << "WARNING: Expected: " << m_atomic_reads << " RMW_Writes, but only received: " << m_atomic_writes << endl;
assert(false);
}
ctype = CacheRequestType_IFETCH;
break;
case RubyRequestType_LD:
if (m_atomic_reads > 0 && m_atomic_writes == 0) {
m_controller->reset_atomics();
}
else if (m_atomic_writes > 0) {
assert(m_atomic_reads > m_atomic_writes);
cerr << "WARNING: Expected: " << m_atomic_reads << " RMW_Writes, but only received: " << m_atomic_writes << endl;
assert(false);
}
ctype = CacheRequestType_LD;
break;
case RubyRequestType_ST:
if (m_atomic_reads > 0 && m_atomic_writes == 0) {
m_controller->reset_atomics();
}
else if (m_atomic_writes > 0) {
assert(m_atomic_reads > m_atomic_writes);
cerr << "WARNING: Expected: " << m_atomic_reads << " RMW_Writes, but only received: " << m_atomic_writes << endl;
assert(false);
}
ctype = CacheRequestType_ST;
break;
case RubyRequestType_Locked_Read:
case RubyRequestType_Locked_Write:
ctype = CacheRequestType_ATOMIC;
break;
case RubyRequestType_RMW_Read:
assert(m_atomic_writes == 0);
m_atomic_reads++;
ctype = CacheRequestType_ATOMIC;
break;
case RubyRequestType_RMW_Write:
assert(m_atomic_reads > 0);
assert(m_atomic_writes < m_atomic_reads);
m_atomic_writes++;
if (m_atomic_reads == m_atomic_writes) {
m_atomic_reads = 0;
m_atomic_writes = 0;
}
ctype = CacheRequestType_ATOMIC;
break;
default:

4
src/mem/ruby/system/Sequencer.hh
View file

@ -125,8 +125,8 @@ private:
// Global outstanding request count, across all request tables
int m_outstanding_count;
bool m_deadlock_check_scheduled;
unsigned m_servicing_atomic;
int m_atomics_counter;
int m_atomic_reads;
int m_atomic_writes;
};
// Output operator declaration

100
src/mem/slicc/symbols/StateMachine.cc
View file

@ -291,8 +291,8 @@ void StateMachine::printControllerH(ostream& out, string component)
out << " void printConfig(ostream& out) const;" << endl;
out << " void wakeup();" << endl;
out << " void set_atomic(Address addr);" << endl;
out << " void started_writes();" << endl;
out << " void clear_atomic();" << endl;
out << " void clear_atomic(Address addr);" << endl;
out << " void reset_atomics();" << endl;
out << " void printStats(ostream& out) const { s_profiler.dumpStats(out); }" << endl;
out << " void clearStats() { s_profiler.clearStats(); }" << endl;
out << "private:" << endl;
@ -876,7 +876,8 @@ void StateMachine::printCWakeup(ostream& out, string component)
} \n \
} \n \
";
output.insert(pos, atomics_string);
// output.insert(pos, atomics_string);
/*string foo = "// Cannot do anything with this transition, go check next doable transition (mostly likely of next port)\n";
string::size_type next_pos = output.find(foo, pos);
next_pos = next_pos + foo.length();
@ -898,13 +899,19 @@ void StateMachine::printCWakeup(ostream& out, string component)
out << " if ((((*m_L1Cache_forwardToCache_ptr)).isReady())) {" << endl;
out << " const RequestMsg* in_msg_ptr;" << endl;
out << " in_msg_ptr = dynamic_cast<const RequestMsg*>(((*m_L1Cache_forwardToCache_ptr)).peek());" << endl;
out << " if ((((servicing_atomic == 1) && (locked_read_request1 == ((*in_msg_ptr)).m_Address)) || " << endl;
out << " ((servicing_atomic == 2) && (locked_read_request1 == ((*in_msg_ptr)).m_Address || locked_read_request2 == ((*in_msg_ptr)).m_Address)) || " << endl;
out << " ((servicing_atomic == 3) && (locked_read_request1 == ((*in_msg_ptr)).m_Address || locked_read_request2 == ((*in_msg_ptr)).m_Address || locked_read_request3 == ((*in_msg_ptr)).m_Address)) || " << endl;
out << " ((servicing_atomic == 4) && (locked_read_request1 == ((*in_msg_ptr)).m_Address || locked_read_request2 == ((*in_msg_ptr)).m_Address || locked_read_request3 == ((*in_msg_ptr)).m_Address || locked_read_request1 == ((*in_msg_ptr)).m_Address)))) {" << endl;
// out << " (locked_read_request2 == ((*in_msg_ptr)).m_Address) || (locked_read_request3 == ((*in_msg_ptr)).m_Address) || " << endl;
// out << " (locked_read_request4 == ((*in_msg_ptr)).m_Address))) { " << endl;
out << " if ((((servicing_atomic > 0) && (locked_read_request1 == ((*in_msg_ptr)).m_Address || locked_read_request2 == ((*in_msg_ptr)).m_Address || locked_read_request3 == ((*in_msg_ptr)).m_Address || locked_read_request1 == ((*in_msg_ptr)).m_Address)))) {" << endl;
out << " postpone = true;" << endl;
out << " }" << endl;
out << " }" << endl;
out << " if (!postpone) {" << endl;
}
else if (port->toString().find("requestNetwork_in") != string::npos || port->toString().find("requestIntraChipL1Network_in") != string::npos) {
out << " bool postpone = false;" << endl;
out << " if ((((*m_L1Cache_requestToL1Cache_ptr)).isReady())) {" << endl;
out << " const RequestMsg* in_msg_ptr;" << endl;
out << " in_msg_ptr = dynamic_cast<const RequestMsg*>(((*m_L1Cache_requestToL1Cache_ptr)).peek());" << endl;
out << " if ((((servicing_atomic > 0) && (locked_read_request1 == ((*in_msg_ptr)).m_Address || locked_read_request2 == ((*in_msg_ptr)).m_Address || locked_read_request3 == ((*in_msg_ptr)).m_Address || locked_read_request1 == ((*in_msg_ptr)).m_Address)))) {" << endl;
out << " postpone = true;" << endl;
out << " }" << endl;
@ -921,6 +928,12 @@ void StateMachine::printCWakeup(ostream& out, string component)
if (port->toString().find("forwardRequestNetwork_in") != string::npos) {
out << "}" << endl;
}
else if (port->toString().find("requestIntraChipL1Network_in") != string::npos) {
out << "}" << endl;
}
else if (port->toString().find("requestNetwork_in") != string::npos) {
out << "}" << endl;
}
}
out << endl;
}
@ -939,37 +952,66 @@ void StateMachine::printCWakeup(ostream& out, string component)
out << "void " << component << "_Controller::set_atomic(Address addr)" << endl;
out << "{" << endl;
out << " servicing_atomic++; " << endl;
out << " switch (servicing_atomic) { " << endl;
out << " case(1): " << endl;
out << " assert(locked_read_request1 == Address(-1)); " << endl;
out << " locked_read_request1 = addr; " << endl;
out << " break; " << endl;
out << " case(2): " << endl;
out << " assert(locked_read_request2 == Address(-1)); " << endl;
out << " locked_read_request2 = addr; " << endl;
out << " break; " << endl;
out << " case(3): " << endl;
out << " assert(locked_read_request3 == Address(-1)); " << endl;
out << " locked_read_request3 = addr; " << endl;
out << " break; " << endl;
out << " case(4): " << endl;
out << " assert(locked_read_request4 == Address(-1)); " << endl;
out << " locked_read_request4 = addr; " << endl;
out << " break; " << endl;
out << " default: " << endl;
out << " assert(0);" << endl;
out << " }" << endl;
out << "}" << endl;
out << "void " << component << "_Controller::started_writes()" << endl;
out << "{" << endl;
out << " started_receiving_writes = true; " << endl;
out << "}" << endl;
out << "void " << component << "_Controller::clear_atomic()" << endl;
out << "void " << component << "_Controller::clear_atomic(Address addr)" << endl;
out << "{" << endl;
out << " assert(servicing_atomic > 0); " << endl;
out << " read_counter--; " << endl;
out << " if (addr == locked_read_request1) " << endl;
out << " locked_read_request1 = Address(-1);" << endl;
out << " else if (addr == locked_read_request2)" << endl;
out << " locked_read_request2 = Address(-1);" << endl;
out << " else if (addr == locked_read_request3)" << endl;
out << " locked_read_request3 = Address(-1);" << endl;
out << " else if (addr == locked_read_request4)" << endl;
out << " locked_read_request4 = Address(-1);" << endl;
out << " else " << endl;
out << " assert(0); " << endl;
out << " servicing_atomic--; " << endl;
out << " if (read_counter == 0) { " << endl;
out << " servicing_atomic = 0; " << endl;
out << " started_receiving_writes = false; " << endl;
out << " locked_read_request1 = Address(-1); " << endl;
out << " locked_read_request2 = Address(-1); " << endl;
out << " locked_read_request3 = Address(-1); " << endl;
out << " locked_read_request4 = Address(-1); " << endl;
out << " } " << endl;
out << "}" << endl;
out << "void " << component << "_Controller::reset_atomics()" << endl;
out << "{" << endl;
out << " assert(servicing_atomic > 0); " << endl;
out << " servicing_atomic = 0; " << endl;
out << " locked_read_request1 = Address(-1);" << endl;
out << " locked_read_request2 = Address(-1);" << endl;
out << " locked_read_request3 = Address(-1);" << endl;
out << " locked_read_request4 = Address(-1);" << endl;
out << "}" << endl;
}
else {
out << "void " << component << "_Controller::started_writes()" << endl;
out << "{" << endl;
out << " assert(0); " << endl;
out << "}" << endl;
out << "void " << component << "_Controller::set_atomic(Address addr)" << endl;
out << "{" << endl;
out << " assert(0); " << endl;
out << "}" << endl;
out << "void " << component << "_Controller::clear_atomic()" << endl;
out << "void " << component << "_Controller::clear_atomic(Address addr)" << endl;
out << "{" << endl;
out << " assert(0); " << endl;
out << "}" << endl;
out << "void " << component << "_Controller::reset_atomics()" << endl;
out << "{" << endl;
out << " assert(0); " << endl;
out << "}" << endl;

2
util/style.py
View file

@ -72,7 +72,7 @@ def format_file(filename):
if file_type(filename) in format_types:
return True
return False
return True
def checkwhite_line(line):
match = lead.search(line)