3079 commits

Author	SHA1	Message	Date
Min Kyu Jeong	5d5bf8cbc7	ARM: Fix IT state not updating when an instruction memory instruction faults.	2010-06-02 12:58:18 -05:00
Dam Sunwoo	4325519fc5	ARM: Allow multiple outstanding TLB walks to queue.	2010-06-02 12:58:18 -05:00
Ali Saidi	2bad5138e4	ARM TLB: Fix bug in memAttrs getting a bogus thread context	2010-06-02 12:58:18 -05:00
Dam Sunwoo	6b00c7fa22	ARM: Support table walks in timing mode.	2010-06-02 12:58:18 -05:00
Dam Sunwoo	6c8dd32fa4	ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PCWUR, V2PCWUW,...)	2010-06-02 12:58:18 -05:00
Gabe Black	85ba2a3243	ARM: Decode the neon instruction space.	2010-06-02 12:58:18 -05:00
Gabe Black	e50e6a260f	ARM: Add a comment to vfp.cc that explains the asm statements.	2010-06-02 12:58:18 -05:00
Gabe Black	10031a0327	ARM: Move some case values out of ##included files. ... This will help keep the high level decode together and not have it spread into the subordinate decode stuff. The ##include lines still need to be on a line by themselves, though.	2010-06-02 12:58:18 -05:00
Gabe Black	22f15ab94e	ARM: Combine some redundant cases in one of the data decode functions.	2010-06-02 12:58:18 -05:00
Gabe Black	fcee2b3f31	ARM: Add comments to the classes in macromem.hh.	2010-06-02 12:58:18 -05:00
Gabe Black	362b747fdc	ARM: Move code from vfp.hh to vfp.cc.	2010-06-02 12:58:18 -05:00
Ali Saidi	35e35fc825	ARM: Make some of the trace code more compact	2010-06-02 12:58:18 -05:00
Gabe Black	0abec53564	ARM: Move the longer MemoryReg::printoffset function in mem.hh into the cc file.	2010-06-02 12:58:18 -05:00
Gabe Black	9223725973	ARM: Move the ISA "clear" function into isa.cc.	2010-06-02 12:58:17 -05:00
Gabe Black	b6c2548a27	ARM: Get rid of the binary dumping function in utility.hh.	2010-06-02 12:58:17 -05:00
Gabe Black	f8d2ed708b	ARM: Get rid of the empty branch.cc.	2010-06-02 12:58:17 -05:00
Gabe Black	0c574987c8	ARM: Mark some ARM static inst functions as inline.	2010-06-02 12:58:17 -05:00
Gabe Black	ba7a7b0394	ARM: Move some predecoder stuff into a .cc file. ... --HG-- rename : src/arch/arm/predecoder.hh => src/arch/arm/predecoder.cc	2010-06-02 12:58:17 -05:00
Gabe Black	358fdc2a40	ARM: Decode to specialized conditional/unconditional versions of instructions. ... This is to avoid condition code based dependences from effectively serializing instructions when the instruction doesn't actually use them.	2010-06-02 12:58:17 -05:00
Gabe Black	596cbe19d4	ARM: Make sure undefined unconditional ARM instructions decode as such.	2010-06-02 12:58:17 -05:00
Gabe Black	6101e1b062	ARM: Implement a version of mcr and mrc that works in user mode.	2010-06-02 12:58:17 -05:00
Gabe Black	e91e6ff9a4	ARM: Hook the misc instructions into the thumb decoder.	2010-06-02 12:58:17 -05:00
Gabe Black	22d1a84509	ARM: Move some miscellaneous instructions out of the decoder to share with thumb.	2010-06-02 12:58:17 -05:00
Gabe Black	0e556e9dfb	ARM: Treat LDRD in ARM with an odd index as an undefined instruction.	2010-06-02 12:58:17 -05:00
Ali Saidi	3dc6a8070e	ARM: fix sizes of structs for ARM Linux	2010-06-02 12:58:17 -05:00
Ali Saidi	d3a519ef0c	ARM: Fixup native trace support and add some v7/recent stack code	2010-06-02 12:58:17 -05:00
Gabe Black	5a6bf8301a	ARM: Detect a bad offset field for the VFP Ldm/Stm instructions in the decoder.	2010-06-02 12:58:17 -05:00
Gabe Black	563db6cb99	ARM: Make sure the upc is zeroed when vectoring to a fault.	2010-06-02 12:58:17 -05:00
Ali Saidi	5d67be7b1e	ARM: Implement the getrusage syscall.	2010-06-02 12:58:17 -05:00
Gabe Black	6e39288be0	ARM: Implement the bkpt instruction.	2010-06-02 12:58:16 -05:00
Gabe Black	e9c8f68c0f	ARM: Make undefined instructions obey predication.	2010-06-02 12:58:16 -05:00
Gabe Black	05bd3eb4ec	ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.	2010-06-02 12:58:16 -05:00
Gabe Black	b93ceef538	ARM: Get rid of some of the old FP implementation.	2010-06-02 12:58:16 -05:00
Ali Saidi	c1e1de8d69	ARM: Some TLB bug fixes.	2010-06-02 12:58:16 -05:00
Ali Saidi	7de7ea3b22	ARM: Move Miscreg functions out of isa.hh	2010-06-02 12:58:16 -05:00
Ali Saidi	cb9936cfde	ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.	2010-06-02 12:58:16 -05:00
Ali Saidi	1546d8208b	ARM: SE needs a definition for PageTable::serialize/unserialize	2010-06-02 12:58:16 -05:00
Ali Saidi	d2ba9243f5	ARM: Add BKPT instruction ... --HG-- rename : src/arch/arm/isa/formats/unknown.isa => src/arch/arm/isa/formats/breakpoint.isa	2010-06-02 12:58:16 -05:00
Ali Saidi	b8ec214553	ARM: Implement ARM CPU interrupts	2010-06-02 12:58:16 -05:00
Ali Saidi	3aea20d143	ARM: Start over with translation from Alpha code as opposed to something that has cruft from 4 different ISAs.	2010-06-02 12:58:16 -05:00
Gabe Black	237c0617a0	ARM: Implement conversion to/from half precision.	2010-06-02 12:58:16 -05:00
Gabe Black	04e196f422	ARM: Clean up VFP	2010-06-02 12:58:16 -05:00
Gabe Black	0fe0390f73	ARM: Clean up the implementation of the VFP instructions.	2010-06-02 12:58:16 -05:00
Gabe Black	c919ab5b4f	ARM: Fix double precision load/store multiple decrement. ... When decrementing, the higher addressed half of a double word is at a 4 byte smaller displacement.	2010-06-02 12:58:15 -05:00
Gabe Black	92bdf57be4	ARM: Even though writes to MVFR0/1 should be unpredictable, we need to make them to do nothing.	2010-06-02 12:58:15 -05:00
Gabe Black	4398075254	ARM: Make various bits of the FP control registers read only.	2010-06-02 12:58:15 -05:00
Gabe Black	2d08b8de91	ARM: Implement the version of VMRS that writes to the APSR.	2010-06-02 12:58:15 -05:00
Gabe Black	57c4d37c10	ARM: Ignore reads and writes to DCIMVAC.	2010-06-02 12:58:15 -05:00
Gabe Black	fd37095fa6	ARM: Make MPIDR return 0 and ignore writes.	2010-06-02 12:58:15 -05:00
Gabe Black	49b7088b91	ARM: Implement the VCMPE instruction.	2010-06-02 12:58:15 -05:00
Gabe Black	23ba9c7b96	ARM: Fix vcvtr so that it uses the rounding mode in the FPSCR.	2010-06-02 12:58:15 -05:00
Gabe Black	1fda944716	ARM: Fix saturation of VCVT from fp to integer.	2010-06-02 12:58:15 -05:00
Gabe Black	347ab6c704	ARM: Compensate for ARM's underflow coming from -before- rounding, but x86's after.	2010-06-02 12:58:15 -05:00
Gabe Black	fd82a47b96	ARM: Implement flush to zero for destinations as well.	2010-06-02 12:58:15 -05:00
Gabe Black	186273e5f3	ARM: Fix up nans to match ARM's expected behavior.	2010-06-02 12:58:15 -05:00
Gabe Black	98e2315f1c	ARM: Set the value of the MVFR0 and MVFR1 registers.	2010-06-02 12:58:15 -05:00
Gabe Black	8466999aef	ARM: Implement flush to zero mode for VFP, and clean up some corner cases.	2010-06-02 12:58:15 -05:00
Gabe Black	efbceff96a	ARM: Add barriers that make sure FP operations happen where they're supposed to.	2010-06-02 12:58:15 -05:00
Gabe Black	1b3b75ee68	ARM: Implement the version of VCVT float to int that rounds towards zero.	2010-06-02 12:58:15 -05:00
Gabe Black	aa05e5401c	ARM: Implement the floating/fixed point VCVT instructions.	2010-06-02 12:58:15 -05:00
Gabe Black	86a1093992	ARM: Add code to extract and record VFP exceptions.	2010-06-02 12:58:14 -05:00
Gabe Black	e478df35f5	ARM: Implement the VFP version of VCMP.	2010-06-02 12:58:14 -05:00
Gabe Black	c1f7bf7f0e	ARM: Add support for VFP vector mode.	2010-06-02 12:58:14 -05:00
Gabe Black	f245f4937b	ARM: Introduce new VFP base classes that are optionally microops.	2010-06-02 12:58:14 -05:00
Gabe Black	41012d2418	ARM: Implement VCVT between double and single width FP.	2010-06-02 12:58:14 -05:00
Gabe Black	a430f749ce	ARM: Implement vcvt between int and fp. Ignore rounding.	2010-06-02 12:58:14 -05:00
Gabe Black	a9d1de4769	ARM: Consolidate the VFP register index computation code.	2010-06-02 12:58:14 -05:00
Gabe Black	80fa3a7ccf	ARM: Implement the VFP negated multiplies.	2010-06-02 12:58:14 -05:00
Gabe Black	3111a62169	ARM: Implement the VFP versions of VMLA and VMLS.	2010-06-02 12:58:14 -05:00
Gabe Black	90d70a22cb	ARM: Implement the VFP version of vdiv and vsqrt.	2010-06-02 12:58:14 -05:00
Gabe Black	cc665240a4	ARM: Implement the VFP version of vsub.	2010-06-02 12:58:14 -05:00
Gabe Black	44759669aa	ARM: Implement the VFP version of vadd.	2010-06-02 12:58:14 -05:00
Gabe Black	9e32ff3491	ARM: Implement the VFP version of vabs.	2010-06-02 12:58:14 -05:00
Gabe Black	cd0a6a1303	ARM: Implement the VFP version of vneg.	2010-06-02 12:58:14 -05:00
Gabe Black	65f5204325	ARM: Implement the VFP version of vmul.	2010-06-02 12:58:14 -05:00
Gabe Black	19e05d7e8d	ARM: Move the VFP data operation decode into a function.	2010-06-02 12:58:14 -05:00
Gabe Black	527b735cfc	ARM: Implement and update the DFSR and IFSR registers on faults.	2010-06-02 12:58:14 -05:00
Gabe Black	4491170df6	ARM: Make integer division by zero return a fault.	2010-06-02 12:58:13 -05:00
Gabe Black	cd86e34187	ARM: Add in some missing SCTLR fields.	2010-06-02 12:58:13 -05:00
Gabe Black	c5a8a1d673	ARM: Decode ARM unconditional MRC and MCR instructions.	2010-06-02 12:58:13 -05:00
Gabe Black	98fe7b0fbe	ARM: Move the CP15 decode block into a function.	2010-06-02 12:58:13 -05:00
Gabe Black	5d9191a428	ARM: Decode the unconditional version of ARM fp instructions.	2010-06-02 12:58:13 -05:00
Gabe Black	81b7c3d264	ARM: Move the FP decode blocks into functions.	2010-06-02 12:58:13 -05:00
Gabe Black	e21f93702a	ARM: Warn/ignore when TLB maintenance operations are performed.	2010-06-02 12:58:13 -05:00
Gabe Black	eac239b4d6	ARM: Handle accesses to TLBTR.	2010-06-02 12:58:13 -05:00
Gabe Black	9fb573d91e	ARM: Handle accesses to the DACR.	2010-06-02 12:58:13 -05:00
Gabe Black	951b7edaba	ARM: Handle accesses to TTBR0 and TTBR1.	2010-06-02 12:58:13 -05:00
Gabe Black	b5cfa9361b	ARM: Convert the CP15 registers from MPU to MMU.	2010-06-02 12:58:13 -05:00
Ali Saidi	556ea0ee57	ARM: Add some support for wfi/wfe/yield/etc	2010-06-02 12:58:13 -05:00
Ali Saidi	5e6d28996a	ARM: Move PC mode bits around so they can be used for exectrace	2010-06-02 12:58:13 -05:00
Ali Saidi	aec73ba6af	ARM: Add a traceflag to print cpsr	2010-06-02 12:58:13 -05:00
Ali Saidi	65a5177b53	ARM: Undef instruction on invalid user CP15 access	2010-06-02 12:58:13 -05:00
Gabe Black	2e4ddbd234	ARM: Decode the VSTR instruction.	2010-06-02 12:58:12 -05:00
Gabe Black	6106bd18cd	ARM: Implement the vstr instruction.	2010-06-02 12:58:12 -05:00
Ali Saidi	f64c8bafd2	ARM: BXJ should be BX when there is no J support	2010-06-02 12:58:12 -05:00
Gabe Black	1fcd389fa3	ARM: Make sure macroops aren't interrupted midinstruction. ... Do this by setting the delayed commit flag for all but the last microop.	2010-06-02 12:58:12 -05:00
Gabe Black	67766cbf17	ARM: Fix the implementation of the VFP ldm and stm macroops. ... There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.	2010-06-02 12:58:12 -05:00
Gabe Black	ad9c5af945	ARM: Fix up thumb decoding of coproc instructions.	2010-06-02 12:58:12 -05:00
Gabe Black	dea707704f	ARM: Clean up some redundancy and fault behavior for unimplemented thumb MCR, MRC.	2010-06-02 12:58:12 -05:00
Gabe Black	943b77b9bb	ARM: Decode the VLDR instruction.	2010-06-02 12:58:12 -05:00
Gabe Black	4f130683e0	ARM: Implement the VLDR instruction.	2010-06-02 12:58:12 -05:00
Gabe Black	dbec303864	ARM: Decode all the various forms of vmov.	2010-06-02 12:58:12 -05:00
Gabe Black	ff3996b24d	ARM: Make VFP load/store and 64 bit move decode correspond with CP10 and CP11.	2010-06-02 12:58:12 -05:00
Gabe Black	dd1aedc98b	ARM: Implement the various versions of VMOV.	2010-06-02 12:58:12 -05:00
Gabe Black	1f059541d6	ARM: Add a new RegImmOp base class.	2010-06-02 12:58:12 -05:00
Gabe Black	6976b4890a	ARM: Add a RegRegImmOp base class.	2010-06-02 12:58:12 -05:00
Gabe Black	186cfe3ae3	ARM: Widen the immediate fields in the misc instruction classes.	2010-06-02 12:58:12 -05:00
Gabe Black	b87ebf382f	ARM: Add a function to decode VFP modified immediate constants.	2010-06-02 12:58:12 -05:00
Gabe Black	7eb4d02dd9	ARM: Add a function to decode SIMD modified immediate constants.	2010-06-02 12:58:12 -05:00
Gabe Black	abda50173c	ARM: Add fp operands to operands.isa.	2010-06-02 12:58:12 -05:00
Gabe Black	6365d29c21	ARM: Decode the VMRS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	fbf2ad5ae8	ARM: Update the set of FP related miscregs.	2010-06-02 12:58:11 -05:00
Gabe Black	aade63a8fe	ARM: Implement the VMRS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	a8b56b452c	ARM: Decode the VMSR instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	06008c54eb	ARM: Implement the VMSR instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	0ff71c7c34	ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.	2010-06-02 12:58:11 -05:00
Gabe Black	c9c4dfc09d	ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.	2010-06-02 12:58:11 -05:00
Gabe Black	c3bf29bbea	ARM: Implement the udiv instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	f3e65c2de2	ARM: Implement the sdiv instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	5943f0fc84	ARM: Ignore writing a bad mode to CPSR with MSR.	2010-06-02 12:58:11 -05:00
Gabe Black	ba33db8fd6	ARM: Decode the CPS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	7861b084f6	ARM: Implement the CPS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	eb1447302d	ARM: Decode the SRS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	bb6fea91da	ARM: Implement the SRS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	dbee6e0c54	ARM: Add a base class for SRS.	2010-06-02 12:58:11 -05:00
Gabe Black	239c9af90d	ARM: Implement a badMode function that says whether a mode is legal.	2010-06-02 12:58:11 -05:00
Gabe Black	a5ea52bb45	ARM: Allow flattening into any mode.	2010-06-02 12:58:11 -05:00
Gabe Black	698ee26c6b	ARM: Decode TBB and TBH.	2010-06-02 12:58:11 -05:00
Gabe Black	6fa713a66c	ARM: Decode the setend instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	4683cd1655	ARM: Define the setend instruction.	2010-06-02 12:58:10 -05:00
Gabe Black	fb23297914	ARM: Make a base class for instructions that use only an immediate.	2010-06-02 12:58:10 -05:00
Gabe Black	247acd93c4	ARM: Decode the arm version of ldrexd.	2010-06-02 12:58:10 -05:00
Gabe Black	3ad31f61c2	ARM: Decode the strex instructions.	2010-06-02 12:58:10 -05:00
Gabe Black	54ab07e636	ARM: Implement the strex instructions.	2010-06-02 12:58:10 -05:00
Gabe Black	524a8195e1	ARM: Set CPSR.E to SCTLR.EE on faults.	2010-06-02 12:58:10 -05:00
Gabe Black	683421e0c6	ARM: Warn about not implementing MPU translation, not panic about MMU. ... We'll start out with a stbu version of PMSA and switch over to VMSA for the full implementation.	2010-06-02 12:58:10 -05:00
Gabe Black	6fb5189c47	ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.	2010-06-02 12:58:10 -05:00
Gabe Black	89b1dd5582	ARM: Allow access to the RGNR register.	2010-06-02 12:58:10 -05:00
Gabe Black	c3381167c9	ARM: Make the MPUIR register report that 1 unified data region is supported.	2010-06-02 12:58:10 -05:00
Gabe Black	3aa8faf177	ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.	2010-06-02 12:58:10 -05:00
Gabe Black	faf6c727f6	ARM: Respect the E bit of the CPSR when doing loads and stores.	2010-06-02 12:58:10 -05:00
Gabe Black	b6cb6f1874	ARM: Zero the micropc when vectoring to a fault.	2010-06-02 12:58:10 -05:00
Gabe Black	1d5233958a	ARM: Implement the V7 version of alignment checking.	2010-06-02 12:58:10 -05:00
Gabe Black	7b397925af	ARM: Decode the RFE instruction.	2010-06-02 12:58:10 -05:00
Gabe Black	a2cb503ba6	ARM: Implement the RFE instruction.	2010-06-02 12:58:10 -05:00
Gabe Black	ec4cd00b11	ARM: Add a base class for the RFE instruction.	2010-06-02 12:58:10 -05:00
Gabe Black	1ada9d4880	ARM: Make sure some undefined thumb32 instructions fault.	2010-06-02 12:58:10 -05:00
Gabe Black	3caa75d53a	ARM: Squash the low order bits of the PC when performing a regular branch.	2010-06-02 12:58:10 -05:00
Gabe Black	36eeee0133	ARM: When changing the CPSR and branching, make sure the branch is second.	2010-06-02 12:58:09 -05:00
Gabe Black	68f2908a70	ARM: Ignore/warn when CSSELR or CCSIDR are accessed. ... These registers provide information about the caches. Since we can't provide that information, these will be harmlessly inert.	2010-06-02 12:58:09 -05:00
Gabe Black	741b243260	ARM: Ignore/warn access to the bpimva registers.	2010-06-02 12:58:09 -05:00
Gabe Black	8a7f60194e	ARM: Ignore/warn on accesses to the dccmvac register.	2010-06-02 12:58:09 -05:00
Gabe Black	89133b15da	ARM: Decode the enterx and leavex instructions.	2010-06-02 12:58:09 -05:00
Gabe Black	6a4ea7cca9	ARM: Implement the enterx and leavex instructions. ... These enter and leave thumbEE mode. Currently thumbEE mode behaves exactly the same as Thumb mode, but at least this will make it -look- like we're enter and leaving it. The actual behavioral changes will be implemented in future changes.	2010-06-02 12:58:09 -05:00
Gabe Black	eb0823c4f2	ARM: Fix the implementation of BX to work in thumbEE mode.	2010-06-02 12:58:09 -05:00
Gabe Black	bb0d390105	ARM: When an instruction is intentionally undefined, fault on it.	2010-06-02 12:58:09 -05:00
Gabe Black	61a5e71be7	ARM: Decode the thumb version of the ldrd and strd instructions.	2010-06-02 12:58:09 -05:00
Gabe Black	9d4a1bf2ba	ARM: Explicitly keep track of the second destination for double loads/stores.	2010-06-02 12:58:09 -05:00
Gabe Black	28023f6f3d	ARM: Decode the thumb32 load byte/memory hint instructions.	2010-06-02 12:58:09 -05:00
Gabe Black	7a9dcdf99f	ARM: Decode the load halfword, memory hints instructions for 32 bit Thumb.	2010-06-02 12:58:09 -05:00
Gabe Black	a483d44d9f	ARM: Ignore/warn on accesses to icimvau.	2010-06-02 12:58:09 -05:00
Gabe Black	630f309a77	ARM: Ignore/warn on iciallu.	2010-06-02 12:58:09 -05:00
Gabe Black	d618121670	ARM: Ignore/warn on ICIALLUIS.	2010-06-02 12:58:09 -05:00
Gabe Black	e658b6fed4	ARM: Add support for the clidr register. ... This register will always report 0 caches as implemented. It's not clear how to find out how many there really are when dealing with an arbitrary hierarchy.	2010-06-02 12:58:09 -05:00
Gabe Black	896c7617c4	ARM: Decode the unimplemented data barrier CP15 accesses. ... These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory Barrier).	2010-06-02 12:58:09 -05:00
Gabe Black	af6b1667e9	ARM: Implement a stub of CPACR. ... This register controls access to the coprocessors. This doesn't actually implement it, it allows writes which don't turn anything off. In other words, it allows the simulated program to ask for what it already has.	2010-06-02 12:58:09 -05:00
Gabe Black	660270746b	ARM: Actually write the value of sctlr in ISA.clear().	2010-06-02 12:58:08 -05:00
Gabe Black	6c9ab5d898	ARM: Replace the ARM decode of CP15 MCR and MRC instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	35f0c01fea	ARM: Decode the unimplemented cp15 instruction barrier.	2010-06-02 12:58:08 -05:00
Gabe Black	7932b86298	ARM: Ignore accesses to DCCIMVAC.	2010-06-02 12:58:08 -05:00
Gabe Black	6ae4d34a12	ARM: Allow accesses to the software thread id registers.	2010-06-02 12:58:08 -05:00
Gabe Black	54850e4d23	ARM: Allow accesses to the contextidr register.	2010-06-02 12:58:08 -05:00
Gabe Black	221e0ac523	ARM: Warn about and ignore accesses to DCCISW. ... This register is supposed to "Clean and invalidate data or unified cache line by set/way." Since there isn't a good way to do that, we'll just ignore these and warn about it.	2010-06-02 12:58:08 -05:00
Gabe Black	8c1be04af6	ARM: Decode the thumb versions of the mcr and mrc instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	625a43e7c7	ARM: Implement the mrc and mcr instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	6c1b10043f	ARM: Rename the RevOp base class to something more generic.	2010-06-02 12:58:08 -05:00
Gabe Black	f9d1bba22a	ARM: Add a version of the Dest and Op1 operands for accessing the MiscRegs.	2010-06-02 12:58:08 -05:00
Gabe Black	6aa229386d	ARM: Implement a function to decode CP15 registers to MiscReg indices.	2010-06-02 12:58:08 -05:00
Gabe Black	7ff24c8777	ARM: Decode the bfi and bfc instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	a37b6b6bce	ARM: Implement the bfc and bfi instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	5a63887617	ARM: Decode the ubfx and sbfx instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	2e717558e2	ARM: Decode miscellaneous arm mode media instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	09cc401848	ARM: Implement the ubfx and sbfx instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	b1158e4938	ARM: Add a register, immediate, immediate to register base for [su]bfx.	2010-06-02 12:58:08 -05:00
Gabe Black	504ac6518b	ARM: Decode the clz instruction.	2010-06-02 12:58:08 -05:00
Gabe Black	2c94bf7f30	ARM: Implement the clz instruction.	2010-06-02 12:58:08 -05:00
Gabe Black	00320a53ab	ARM: Decode the rbit instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	5cc1bb6842	ARM: Implement the rbit instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	566b2ff20c	ARM: Decode the nop instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	b9cfe9a3db	ARM: Implement nop.	2010-06-02 12:58:07 -05:00
Gabe Black	a2d8dcebba	ARM: Decode the ldrex instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	952253483b	ARM: Rearrange the load/store double/exclusive, table branch thumb decoding.	2010-06-02 12:58:07 -05:00
Gabe Black	f7f75ad053	ARM: Implement the ldrex instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	00baeb742d	ARM: Decode the usad8 and usada8 instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	8f566e5ee3	ARM: Implement the usad8 and usada8 instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	c643b1c274	ARM: Add a base class to support usada8.	2010-06-02 12:58:07 -05:00
Gabe Black	64ade8316e	ARM: Decode the sel instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	7fa6835a0c	ARM: Implement the sel instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	498f9d925e	ARM: Add a base class for the sel instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	f581fd3f89	ARM: Decode pkh instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	9ffc5e2ae6	ARM: Implement the pkh instruction.	2010-06-02 12:58:07 -05:00
Gabe Black	c4d09747a5	ARM: Decode the sign/zero extend instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	69365876d8	ARM: Implement zero/sign extend instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	554fb3774e	ARM: Add a base class for extend and add instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	cb2e3b0ace	ARM: Generalize the saturation instruction bases for use in other instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	a1208aa66d	ARM: Decode the 8/16 bit signed/unsigned add/subtract half instructions.	2010-06-02 12:58:07 -05:00
Gabe Black	cabf766a06	ARM: Implement the 8/16 bit signed/unsigned add/subtract half instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	82614b6f3a	ARM: Fix signed most significant multiply instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	3cff58602a	ARM: Fix multiply overflow flag setting.	2010-06-02 12:58:06 -05:00
Gabe Black	90c2284714	ARM: Decode the saturation instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	61b8e33225	ARM: Implement the saturation instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	c96f03a250	ARM: Implement base classes for the saturation instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	0aff168f1a	ARM: Decode the signed add/subtract and subtract/add instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	8ba812f1fb	ARM: Implement signed add/subtract and subtract/add.	2010-06-02 12:58:06 -05:00
Gabe Black	a895514d35	ARM: Decode the unsigned 8 and 16 bit add and subtract instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	3f12eb02ab	ARM: Implement the unsigned 8 bit and 16 bit vector adds and subtracts.	2010-06-02 12:58:06 -05:00
Gabe Black	29acf9516c	ARM: Decode the unsigned saturating instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	be888e67e7	ARM: Implement the unsigned saturating instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	5495ebd68d	ARM: Decode the ssub instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	fd6e9f304e	ARM: Implement the ssub instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	bcf0454864	ARM: Decode the SADD8 and SADD16 instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	87975aa691	ARM: Implement the SADD8 and SADD16 instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	d70c31437a	ARM: Support instructions that set the GE bits when they write the condition codes.	2010-06-02 12:58:06 -05:00
Gabe Black	e32aaefe8c	ARM: Decode 32 bit thumb data processing register instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	f19b605aed	ARM: Decode the 16 bit thumb versions of the REV* instructions.	2010-06-02 12:58:06 -05:00
Gabe Black	15356af288	ARM: Decode the ARM version of the REV* instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	59c726b6f4	ARM: Pull decoding of ARM pack, unpack, saturate and reverse instructions into a format.	2010-06-02 12:58:05 -05:00
Gabe Black	aa8493d7d1	ARM: Implement the REV* instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	c981a4de2b	ARM: Add base classes suitable for the REV* instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	57443a2144	ARM: Make LDM that loads the PC perform an interworking branch.	2010-06-02 12:58:05 -05:00
Gabe Black	1344fc2668	ARM: Decode the swp and swpb instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	e157b1f52a	ARM: Implement the swp and swpb instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	1884ed65bd	ARM: Decode MRS and MSR for thumb.	2010-06-02 12:58:05 -05:00
Gabe Black	ff3b21bc2b	ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones.	2010-06-02 12:58:05 -05:00
Gabe Black	f0811eb208	ARM: Define versions of MSR and MRS outside the decoder.	2010-06-02 12:58:05 -05:00
Gabe Black	f61bb9adb9	ARM: Hook up the push/pop versions of stm/ldm in thumb.	2010-06-02 12:58:05 -05:00
Gabe Black	a76ab8e040	ARM: Hook SVC into the thumb decoder.	2010-06-02 12:58:05 -05:00
Gabe Black	cbdebf852e	ARM: Implement SVC (was SWI) outside of the decoder.	2010-06-02 12:58:05 -05:00
Gabe Black	34032f97d6	ARM: Trigger system calls from the SupervisorCall invoke method. ... This simplifies the decoder slightly, and makes the system call mechanism very slightly more realistic.	2010-06-02 12:58:05 -05:00
Gabe Black	52460938cb	ARM: Fix multiply operations. ... These fixes were provided by Ali and fix the saturation condition code and various multiply instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	4fb6fcd82d	ARM: Decode the scalar saturating add/subtract instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	30dd622622	ARM: Decode the parallel add and subtract instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	62e8487d57	ARM: Implement signed saturating add and/or subtract instructions.	2010-06-02 12:58:05 -05:00
Gabe Black	a1253ec644	ARM: Implemented prefetch instructions/decoding (pli, pld, pldw).	2010-06-02 12:58:05 -05:00
Gabe Black	61b00d3224	ARM: Decode unconditional ARM instructions.	2010-06-02 12:58:04 -05:00
Gabe Black	b6e2f5d33f	ARM: Make sure ldm exception return writes back its base in the right mode. ... This change moves the writeback of load multiple instructions to the beginning of the macroop. That way, the MicroLdrRetUop that changes the mode will necessarily happen later, ensuring the writeback happens in the original mode. The actual value in the base register if it also shows up in the register list is undefined, so it's fine if it gets clobbered by one of the loads. For stores where the base register is the lowest numbered in the register list, the original value should be written back. That means stores can't write back at the beginning, but the mode changing problem doesn't affect them so they can continue to write back at the end.	2010-06-02 12:58:04 -05:00
Gabe Black	89060f1fd8	ARM: Rework how unrecognized/unimplemented instructions are handled. ... Instead of panic immediately when these instructions are executed, an UndefinedInstruction fault is returned. In FS mode (not currently implemented), this is the fault that should, to my knowledge, be triggered in these situations and should be handled using the normal architected mechanisms. In SE mode, the fault causes a panic when it's invoked that gives the same information as the instruction did. When/if support for speculative execution of ARM is supported, this will allow a mispeculated and unrecognized and/or unimplemented instruction from causing a panic. Only once the instruction is going to be committed will the fault be invoked, triggering the panic.	2010-06-02 12:58:04 -05:00
Gabe Black	aa45fafb2e	ARM: Add support for "SUBS PC, LR and related instructions".	2010-06-02 12:58:04 -05:00
Gabe Black	2419903dc0	ARM: Make ldrs into the PC and ldm exception return do interworking branches.	2010-06-02 12:58:04 -05:00
Gabe Black	28227440a7	ARM: Align the PC when using it as the base for a load.	2010-06-02 12:58:04 -05:00
Gabe Black	d63f748b53	ARM: Implement ADR as separate from ADD.	2010-06-02 12:58:04 -05:00
Gabe Black	e92dc21fde	ARM: Add support for interworking branch ALU instructions.	2010-06-02 12:58:04 -05:00
Gabe Black	11c3361be4	ARM: Fix when the flag bits are updated for thumb.	2010-06-02 12:58:04 -05:00
Gabe Black	14d25fbad0	ARM: Don't rely on undefined behavior to get arithmetic right shift. ... Shifting to the right of a signed value when the MSB is one is technically undefined behavior, even though in my experience it's done the "right thing" and sign extended the value. This replaces the arithmetic right shift code in ARM that uses that coincidence with some code that relies on bit math.	2010-06-02 12:58:04 -05:00
Gabe Black	05d880f7a1	ARM: Restrict the shift amount from a register to 8 bits. ... The shift amount when taken from a register is supposed to be truncated to an 8 bit value.	2010-06-02 12:58:04 -05:00
Gabe Black	9ebaf8ecd5	ARM: Define the VFP load/store multiple instructions.	2010-06-02 12:58:04 -05:00
Gabe Black	3f83094af2	ARM: Decode the VFP load/store multiple instructions.	2010-06-02 12:58:04 -05:00
Gabe Black	647edea970	ARM: Fix the constant describing the number of floating point registers.	2010-06-02 12:58:04 -05:00
Gabe Black	2f3102f1ef	ARM: Add templates for VFP load/store multiple instructions.	2010-06-02 12:58:04 -05:00
Gabe Black	739f23c64c	ARM: Add base classes for VFP load/store multiple.	2010-06-02 12:58:04 -05:00
Gabe Black	cb631d87c3	ARM: Add floating point load/store microops.	2010-06-02 12:58:04 -05:00
Gabe Black	3a11412c99	ARM: Add an fp version of one of the microop indexed registers.	2010-06-02 12:58:04 -05:00
Gabe Black	d5aee75efe	ARM: Move the mmap region to where Linux actually has it.	2010-06-02 12:58:04 -05:00
Gabe Black	a8eb9d521c	ARM: Eliminate the unused rhi and rlo operands.	2010-06-02 12:58:03 -05:00
Gabe Black	b02c7f1bcd	ARM: Move the macro mem constructor out of the isa desc. ... This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code.	2010-06-02 12:58:03 -05:00
Gabe Black	7b62e9ad71	ARM: Make macroops panic if executed directly. ... The macroop should never be executed, only it's microops will.	2010-06-02 12:58:03 -05:00
Ali Saidi	8fadf2691d	ARM: GCC < 4.3 has some issues with attribute no return on some functions. Fix so it works for older gccs.	2010-06-02 12:58:03 -05:00
Gabe Black	f18040a205	ARM: Split out the "basic" templates and format. ... --HG-- rename : src/arch/arm/isa/formats/basic.isa => src/arch/arm/isa/templates/basic.isa	2010-06-02 12:58:03 -05:00
Gabe Black	c175f1b993	ARM: Remove unnecessary cruft from includes.isa.	2010-06-02 12:58:03 -05:00
Gabe Black	e29ec7d2ed	ARM: Move the inst2string function out of the isa_desc. ... Delete the now empty formats/util.isa.	2010-06-02 12:58:03 -05:00
Gabe Black	ae135228fc	ARM: Get rid of the unused ArmGenericCodeSubs.	2010-06-02 12:58:03 -05:00
Gabe Black	8c012e9571	ARM: Make the predecoder print out the ExtMachInst it gathered when traced.	2010-06-02 12:58:03 -05:00
Gabe Black	458bd025d4	ARM: Remove special naming for the new version of multiply.	2010-06-02 12:58:03 -05:00
Gabe Black	2196f75a25	ARM: Hook the new multiply instructions into all the decoders.	2010-06-02 12:58:03 -05:00
Gabe Black	33da368e99	ARM: Implement all integer multiply instructions.	2010-06-02 12:58:03 -05:00
Gabe Black	50229be27f	ARM: Add templates for multiply instructions.	2010-06-02 12:58:03 -05:00
Gabe Black	3430b34cff	ARM: Add base classes for multiply instructions.	2010-06-02 12:58:03 -05:00
Gabe Black	c7d2f43641	ARM: Decode plain binary immediate thumb data processing instructions.	2010-06-02 12:58:03 -05:00
Gabe Black	dcf218155d	ARM: Define a new "movt" data processing instruction.	2010-06-02 12:58:03 -05:00
Gabe Black	b615ed1470	ARM: Hook the new branch instructions into the 32 bit thumb decoder.	2010-06-02 12:58:03 -05:00
Gabe Black	274badd201	ARM: Hook the new branch instructions into the 16 bit thumb decoder.	2010-06-02 12:58:03 -05:00
Gabe Black	b6b2f8891a	ARM: Eliminate the old style branch instructions.	2010-06-02 12:58:03 -05:00
Gabe Black	d082705b01	ARM: Hook the new branch instructions into the ARM decoder.	2010-06-02 12:58:02 -05:00
Gabe Black	9869343636	ARM: Implement branch instructions external to the decoder.	2010-06-02 12:58:02 -05:00
Gabe Black	a6c1c8debb	ARM: Add new templates for branch instructions.	2010-06-02 12:58:02 -05:00
Gabe Black	ef3972eaae	ARM: Implement new base classes for branches.	2010-06-02 12:58:02 -05:00
Gabe Black	769f3406fe	ARM: Replace the interworking branch base class with a special operand.	2010-06-02 12:58:02 -05:00
Gabe Black	b6e7029dd5	ARM: Fix PC operand handling.	2010-06-02 12:58:02 -05:00
Gabe Black	7eb3ea2798	ARM: Remove the special naming from the new version of data processing instructions.	2010-06-02 12:58:02 -05:00
Gabe Black	4f08b52af2	ARM: Get rid of unnecessary flag calculating functions.	2010-06-02 12:58:02 -05:00
Gabe Black	bf903ec9a1	ARM: Get rid of the unused Jump format.	2010-06-02 12:58:02 -05:00
Gabe Black	36ca0658a4	ARM: Get rid of obsoleted predicated inst formats, etc.	2010-06-02 12:58:02 -05:00
Gabe Black	7939b48265	ARM: Implement disassembly for the new data processing classes.	2010-06-02 12:58:02 -05:00
Gabe Black	b66e3aec43	ARM: Hook the external data processing instructions into the Thumb decoder.	2010-06-02 12:58:02 -05:00
Gabe Black	beb759912b	ARM: Move the modified_imm function from all ARM instructions to just data processing ones.	2010-06-02 12:58:02 -05:00
Gabe Black	8136cb3605	ARM: Hook the new external data processing instructions to the ARM decoder.	2010-06-02 12:58:02 -05:00
Gabe Black	bf45d44cbe	ARM: Implement data processing instructions external to the decoder.	2010-06-02 12:58:02 -05:00
Gabe Black	c02f9cdddf	ARM: Add new base classes for data processing instructions.	2010-06-02 12:58:02 -05:00
Gabe Black	1e7b317a98	ARM: Hook up 32 bit thumb load/store multiple.	2010-06-02 12:58:02 -05:00
Gabe Black	64d6b6ebfd	ARM: Hook up 16 bit thumb load/store multiple.	2010-06-02 12:58:02 -05:00
Gabe Black	51bde086d5	ARM: Reimplement load/store multiple external to the decoder. ... --HG-- rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/insts/macromem.isa rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/templates/macromem.isa	2010-06-02 12:58:02 -05:00
Gabe Black	93a3714816	ARM: Move the templates for predicated instructions into a separate file. ... This allows the templates to all be available at the same time before any of the formats, etc. This breaks an artificial circular dependence. --HG-- rename : src/arch/arm/isa/formats/pred.isa => src/arch/arm/isa/templates/pred.isa	2010-06-02 12:58:01 -05:00
Gabe Black	04300e33d4	ARM: Remove the special naming for the new memory instructions. ... These are the only memory instructions now.	2010-06-02 12:58:01 -05:00
Gabe Black	deb6e8f805	ARM: Eliminate the old memory formats which are no longer used.	2010-06-02 12:58:01 -05:00
Gabe Black	1905024766	ARM: Eliminate decoding for the very deprecated FPA instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	55465844dc	ARM: Make the addressing mode 3 loads/stores use the externally defined instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	36b6ca2ce3	ARM: Pull double memory instructions out of the decoder.	2010-06-02 12:58:01 -05:00
Gabe Black	79b288f7b5	ARM: Force the condition code for 16 bit thumb instructions to be unconditional. ... Before, because 16 bit thumb instructions didn't set the upper 16 bits of the ExtMachInst, that field would be interpretted as "equals".	2010-06-02 12:58:01 -05:00
Gabe Black	a86491fbf2	ARM: Decode 16 bit thumb PC relative memory instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	dc8af1b211	ARM: Decode 16 bit thumb immediate addressed memory instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	4bbd73649d	ARM: Decode 16 bit thumb register addressed memory instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	462cf6f49b	ARM: Make single stores decode to the new external store instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	3b0f3b1ee2	ARM: Add a .w to the disassembly of 32 bit thumb instructions. ... This isn't technically correct since the .w should only be added if there are 32 and 16 bit encodings, but always having it always is better than never having it.	2010-06-02 12:58:01 -05:00
Gabe Black	fde3c8f41d	ARM: Make 32 bit thumb use the new, external load instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	3b93015304	ARM: Define the store instructions from outside the decoder. ... --HG-- rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa	2010-06-02 12:58:01 -05:00
Gabe Black	81fdced83f	ARM: Define the load instructions from outside the decoder.	2010-06-02 12:58:01 -05:00
Gabe Black	321d3a6e8c	ARM: Implement a new set of base classes for non macro memory instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	8933857af7	ARM: Create a "decoder" directory for the files implementing the decoder. ... --HG-- rename : src/arch/arm/isa/armdecode.isa => src/arch/arm/isa/decoder/arm.isa rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/decoder/decoder.isa rename : src/arch/arm/isa/thumbdecode.isa => src/arch/arm/isa/decoder/thumb.isa rename : src/arch/arm/isa/vfpdecode.isa => src/arch/arm/isa/decoder/vfp.isa	2010-06-02 12:58:01 -05:00
Gabe Black	4ebd44dc4f	ARM: Flesh out the 32 bit thumb store single instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	386424ccb5	ARM: Implement the 32 bit thumb load word instructions.	2010-06-02 12:58:01 -05:00
Gabe Black	292b8a3c91	ARM: Add an operand for accessing the current PC.	2010-06-02 12:58:00 -05:00
Gabe Black	003346077f	ARM: Flesh out 32 bit thumb load word decoding.	2010-06-02 12:58:00 -05:00
Gabe Black	0d4c4cacab	ARM: Implement some 32 bit thumb data processing immediate instructions.	2010-06-02 12:58:00 -05:00
Gabe Black	bd8812cf99	ARM: Replace the "never" condition with the "unconditional" condition.	2010-06-02 12:58:00 -05:00
Gabe Black	af91d27271	ARM: Add a base class for 32 bit thumb data processing immediate instructions.	2010-06-02 12:58:00 -05:00
Gabe Black	bfe1a194dd	ARM: Add a function to decode 32 bit thumb immediate values.	2010-06-02 12:58:00 -05:00
Gabe Black	0116655674	ARM: Expand the decoding for 32 bit thumb data processing immediate instructions.	2010-06-02 12:58:00 -05:00
Gabe Black	cef2e8ecee	ARM: Stub out the 32 bit Thumb portion of the decoder.	2010-06-02 12:58:00 -05:00
Gabe Black	659f8d021f	ARM: Add bitfields for 32 bit thumb.	2010-06-02 12:58:00 -05:00
Gabe Black	bc6ae010c9	ARM: Decode VFP instructions.	2010-06-02 12:58:00 -05:00
Gabe Black	7b8525287d	ARM: Stub out the 16 bit thumb decoder.	2010-06-02 12:58:00 -05:00
Gabe Black	aaa619ea23	ARM: Add thumb bitfields to the ExtMachInst and the isa definition.	2010-06-02 12:58:00 -05:00
Gabe Black	a1838f2c79	ARM: Make the decoder handle thumb instructions separately. ... --HG-- rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/armdecode.isa rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/thumbdecode.isa	2010-06-02 12:58:00 -05:00
Gabe Black	0dffd8ce79	ARM: Add a thumb bit bitfield.	2010-06-02 12:58:00 -05:00
Gabe Black	96be7e16c1	ARM: Make the predecoder handle Thumb instructions.	2010-06-02 12:58:00 -05:00
Gabe Black	f49cdb4f5d	ARM: Make sure ExtMachInst is used consistently instead of regular MachInst.	2010-06-02 12:58:00 -05:00
Gabe Black	330d9d4dbc	ARM: Add a bitfield for setting the regular, inst bits of an ExtMachInst.	2010-06-02 12:58:00 -05:00
Gabe Black	a59d219989	ARM: Add a bit to the ExtMachInst to select thumb mode.	2010-06-02 12:58:00 -05:00
Gabe Black	4ddeceba96	ARM: Allow ARM processes to start in Thumb mode.	2010-06-02 12:58:00 -05:00
Gabe Black	ebb273bb7b	ARM: Add a new base class for instructions that can do an interworking branch.	2010-06-02 12:57:59 -05:00
Gabe Black	9ef82c0bc4	ARM: Track the current ISA mode using the PC.	2010-06-02 12:57:59 -05:00
Gabe Black	1c0d9806e5	ARM: Fix custom writer/reader code for non indexed operands.	2010-06-02 12:57:59 -05:00
Gabe Black	4b87bc887a	ARM: Remove IsControl from operands that don't imply control transfers. ... Also remove IsInteger from CondCodes.	2010-06-02 12:57:59 -05:00
Nathan Binkert	bb589d463b	x86: put back code that I accidentally deleted	2010-05-25 20:15:44 -07:00
Nathan Binkert	13d64906c2	copyright: Change HP copyright on x86 code to be more friendly	2010-05-23 22:44:15 -07:00
Gabe Black	c5c559b6ab	SPARC: Implement the version of movcc that uses the fp condition codes.	2010-05-14 14:22:51 -07:00
Gabe Black	c4497dbf03	X86: Make the cvti2f microop sign extend its integer source correctly. ... The code was using the wrong bit as the sign bit. Other similar bits of code seem to be correct.	2010-05-12 00:51:35 -07:00
Gabe Black	cc76842f83	X86: Actual change that fixes div. How did that happen?	2010-05-12 00:49:12 -07:00
Gabe Black	2ee7a89209	X86: Update the base aux vector X86 processes install.	2010-05-03 00:44:08 -07:00
Gabe Black	7524fdda6a	X86: Sometimes CPUID depends on ecx, so pass that in.	2010-05-02 00:40:17 -07:00
Gabe Black	51a3d65e25	X86: Finally fix a division corner case. ... When doing an unsigned 64 bit division with a divisor that has its most significant bit set, the division code would spill a bit off of the end of a uint64_t trying to shift the dividend into position. This change adds code that handles that case specially by purposefully letting it spill and then going ahead assuming there was a 65th one bit.	2010-05-02 00:39:29 -07:00
Nathan Binkert	e99828b06a	tick: rename Clock namespace to SimClock	2010-04-15 16:24:12 -07:00
Steve Reinhardt	4d77ea7a57	cpu: fix exec tracing memory corruption bug ... Accessing traceData (to call setAddress() and/or setData()) after initiating a timing translation was causing crashes, since a failed translation could delete the traceData object before returning. It turns out that there was never a need to access traceData after initiating the translation, as the traced data was always available earlier; this ordering was merely historical. Furthermore, traceData->setAddress() and traceData->setData() were being called both from the CPU model and the ISA definition, often redundantly. This patch standardizes all setAddress and setData calls for memory instructions to be in the CPU models and not in the ISA definition. It also moves those calls above the translation calls to eliminate the crashes.	2010-03-23 08:50:57 -07:00
Nathan Binkert	1068ca85d0	scons: import ply to work around scons sys.path weirdness	2010-03-10 15:39:34 -08:00
Nathan Binkert	f0b4259e98	cpu_models: get rid of cpu_models.py and move the stuff into SCons	2010-02-26 18:14:48 -08:00
Nathan Binkert	ac106767c8	isa_parser: Make SCons import the isa_parser ... this is instead of forking a new interpreter	2010-02-26 18:14:48 -08:00
Nathan Binkert	629e8df196	isa_parser: move the operand map stuff into the ISAParser class.	2010-02-26 18:14:48 -08:00
Nathan Binkert	4db57edade	isa_parser: move more support functions into the ISAParser class	2010-02-26 18:14:48 -08:00
Nathan Binkert	5ad139375e	isa_parser: move more stuff into the ISAParser class	2010-02-26 18:14:48 -08:00
Nathan Binkert	4ef6e129d6	isa_parser: move the formatMap and exportContext into the ISAParser class	2010-02-26 18:14:48 -08:00
Nathan Binkert	4e105f6fe1	isa_parser: Make stack objects class members instead of globals	2010-02-26 18:14:48 -08:00
Nathan Binkert	b4178b1ae7	isa_parser: add a debug variable that changes how errors are reported. ... This allows us to get tracebacks in certain cases where they're more useful than our error message.	2010-02-26 18:14:48 -08:00
Nathan Binkert	40a05f04fb	isa_parser: Use an exception to flag error ... This allows the error to propagate more easily	2010-02-26 18:14:48 -08:00
Nathan Binkert	f82a92925c	isa_parser: Move more stuff into the ISAParser class	2010-02-26 18:14:48 -08:00
Nathan Binkert	f7a627338c	isa_parser: move code around to prepare for putting more stuff in the class	2010-02-26 18:14:48 -08:00
Nathan Binkert	eb4ce01056	isa_parser: simple fixes, formatting and style	2010-02-26 18:14:48 -08:00
Timothy M. Jones	29e8bcead5	O3PCU: Split loads and stores that cross cache line boundaries. ... When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them.	2010-02-12 19:53:20 +00:00
Timothy M. Jones	dd60902152	Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.	2010-02-12 19:53:19 +00:00
Nathan Binkert	8a3fbbd8d9	compile: compile on 32 bit hardware	2009-11-05 17:21:26 -08:00
Nathan Binkert	52ccfde2cd	isa_parser: allow negative integer literals	2009-11-05 17:21:25 -08:00
Lisa Hsu	d6da172517	util: do checkpoint aggregation more cleanly, fix last changeset. ... 1) Move alpha-specific code out of page_table.cc:serialize(). 2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up. 3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN. 4) Fix the memory unserialize that I forgot somehow in the last changeset. 5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py. Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.	2010-01-19 22:03:44 -08:00
Matt DeVuyst	18dc80e07b	MIPS: Beef up process initialization.	2009-12-31 15:30:51 -05:00
Gabe Black	ecaa7070e6	MIPS: Implement the SE mode version of rdhwr.	2009-12-31 15:30:51 -05:00
Gabe Black	c70f3c93af	MIPS: Fix decoding of the rdhwr instruction.	2009-12-31 15:30:51 -05:00
Gabe Black	134937b594	MIPS: Implement the set_thread_area system call.	2009-12-31 15:30:50 -05:00
Gabe Black	d3ed32b989	MIPS: Create an artificial control register to hold the thread pointer. ... In Linux, the set_thread_area system call stores the address of the thread local storage area into a field of the current thread_info structure. Later, to access that value, the program uses the rdhwr instruction to read a "hardware register" with index 29. The 64 bit MIPS manual, volume II, says that index 29 is reserved for a future ABI extension and should cause a "Reserved Instruction Exception". In Linux (and potentially other ISAs) that exception is trapped and emulated to return the value stored by set_thread_area as if that were actually stored by a physical register. The tp_value address (as named in the Linux kernel) is ironically stored as a control register so that it goes with a particular ThreadContext. Syscall emulation will use that to emulate storing to the OS's thread info structure, and rdhwr will emulate faulting and returning that value from software by returning the value itself, as if it was in hardware. In other words, we fake faking the register in SE mode. In an FS mode implementation it should work as specified in the manual.	2009-12-31 15:30:50 -05:00
Gabe Black	cc07dcf026	MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg. ... The MIPS ISA object expects to be constructed with a CPU pointer it uses to look at other thread contexts and allow them to be manipulated with control registers. Unfortunately, that differs from all the other ISA classes and would complicate their implementation. This change makes the event constructor use a CPU pointer pulled out of the thread context passed to setMiscReg instead.	2009-12-31 15:30:50 -05:00
Gabe Black	1261f1d8db	MIPS: Add missing syscall slots. ... These are all after the existing ones, suggesting they were added after the original list was created.	2009-12-21 14:59:40 -08:00
Soumyaroop Roy	1bd0f772f1	Alpha: Implement MVI and remaining BWX instructions.	2009-12-20 15:03:23 -06:00
Gabe Black	c7ca1d3c8a	X86: Add a common named flag for signed media operations.	2009-12-19 01:48:31 -08:00
Gabe Black	2554511533	X86: Create a common flag with a name to indicate high multiplies.	2009-12-19 01:48:07 -08:00
Gabe Black	e474079ddc	X86: Create a common flag with a name to indicate scalar media instructions.	2009-12-19 01:47:30 -08:00
Ali Saidi	422f0d9f10	ARM: Begin implementing CP15	2009-11-17 18:02:09 -06:00
Ali Saidi	0916c376a9	ARM: Differentiate between LDM exception return and LDM user regs.	2009-11-17 18:02:08 -06:00
Ali Saidi	1470dae8e9	ARM: Boilerplate full-system code. ... --HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh	2009-11-17 18:02:08 -06:00
Ali Saidi	171e7f7b24	imported patch isa_fixes2.diff	2009-11-16 11:37:03 -06:00
Gabe Black	9127ee5ac8	ARM: Make the exception return form of ldm restore CPSR.	2009-11-15 00:23:14 -08:00
Gabe Black	903fb8c73d	ARM: Create a new type of load uop that restores spsr into cpsr.	2009-11-15 00:15:42 -08:00
Gabe Black	b41725f723	ARM: Check in the actual change from the last commit. ... The last commit was somehow empty. This was what was supposed to go in it.	2009-11-14 21:03:10 -08:00
Gabe Black	c4042985d7	ARM: Fix up the implmentation of the msr instruction.	2009-11-14 19:22:30 -08:00
Gabe Black	e2ab64543b	ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.	2009-11-14 19:22:30 -08:00
Gabe Black	425ebf6bd7	ARM: Add a bitfield to indicate if an immediate should be used.	2009-11-14 19:22:30 -08:00
Gabe Black	e543f16247	ARM: Write some functions to write to the CPSR and SPSR for instructions.	2009-11-14 19:22:30 -08:00
Gabe Black	812e390693	ARM: Fix up the implmentation of the mrs instruction.	2009-11-14 19:22:29 -08:00
Gabe Black	1df0025e28	ARM: More accurately describe the effects of using the control operands.	2009-11-14 19:22:29 -08:00
Gabe Black	50b9149c75	ARM: Hook up the moded versions of the SPSR. ... These registers can be accessed directly, or through MISCREG_SPSR which will act as whichever SPSR is appropriate for the current mode.	2009-11-14 19:22:29 -08:00
Ali Saidi	48bc573f5f	ARM: Move around decoder to properly decode CP15	2009-11-14 11:25:00 -06:00
Vince Weaver	8f6744c19c	X86: add ULL to 1's being shifted in 64-bit values ... Some of the micro-ops weren't casting 1 to ULL before shifting, which can cause problems. On the perl makerand input this caused some values to be negative that shouldn't have been. The casts are done as ULL(1) instead of 1ULL to match others in the m5 code base.	2009-11-11 17:49:09 -05:00
Gabe Black	5524af83ef	ARM: Fix some bugs in the ISA desc and fill out some instructions.	2009-11-10 23:44:05 -08:00
Gabe Black	850eb54a7c	Merge with the head.	2009-11-10 21:12:53 -08:00
Gabe Black	b8120f6c38	Mem: Eliminate the NO_FAULT request flag.	2009-11-10 21:10:18 -08:00
Gabe Black	2e28da5583	ARM: Implement fault classes. ... Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.	2009-11-10 20:34:38 -08:00
Gabe Black	4779020e13	ARM: Fix the integer register indexes. ... The PC indexes in the various register sets was defined in the section for unaliased registers which was throwing off the indexing. This moves those where they belong. Also, to make detecting accesses to the PC easier and because it's in the same place in all modes, the intRegForceUser function now passes it through as index 15.	2009-11-10 20:19:55 -08:00
Vince Weaver	53e27c0277	X86: Fix bugs in movd implementation. ... Unfortunately my implementation of the movd instruction had two bugs. In one case, when moving a 32-bit value into an xmm register, the lower half of the xmm register was not zero extended. The other case is that xmm was used instead of xmmlm as the source for a register move. My test case didn't notice this at first as it moved xmm0 to eax, which both have the same register number.	2009-11-10 11:29:30 -05:00
Vince Weaver	e81cc233a6	X86: Remove double-cast in Cvtf2i micro-op ... This double cast led to rounding errors which caused some benchmarks to get the wrong values, most notably lucas which failed spectacularly due to CVTTSD2SI returning an off-by-one value. equake was also broken.	2009-11-10 11:18:23 -05:00
Gabe Black	bbbfdee2ed	X86: Don't panic on faults on prefetches in SE mode.	2009-11-08 22:49:58 -08:00
Gabe Black	44e912c6bd	X86: Explain what really didn't work with unmapped addresses in SE mode.	2009-11-08 22:49:57 -08:00
Gabe Black	53086dfefe	X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE.	2009-11-08 22:49:57 -08:00
Nathan Binkert	b1a1f9aec8	automerge	2009-11-08 20:15:54 -08:00
Gabe Black	8a4af3668d	ARM: Support forcing load/store multiple to use user registers.	2009-11-08 15:49:03 -08:00
Gabe Black	bb903b6514	ARM: Simplify the load/store multiple generation code. ... Specifically, get rid of the big switch statement so more cases can be handled. Enumerating all the possible settings doesn't scale well. Also do some minor style clean up.	2009-11-08 15:16:59 -08:00
Nathan Binkert	708faa7677	compile: wrap 64bit numbers with ULL() so 32bit compiles work ... In the isa_parser, we need to check case statements.	2009-11-08 13:31:59 -08:00
Gabe Black	48525f581c	ARM: Split the condition codes out of the CPSR. ... This allows those bits to be renamed while allowing the other fields to control the behavior of the processor.	2009-11-08 02:08:40 -08:00
Gabe Black	d188821d37	ARM: Add in more bits for the mon mode.	2009-11-08 02:01:02 -08:00
Gabe Black	3a3e846151	ARM: Get rid of NumInternalProcRegs. ... That constant is a carry over from Alpha and doesn't do anything in ARM.	2009-11-08 02:00:55 -08:00
Gabe Black	78bd8fe44f	ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.	2009-11-08 01:59:20 -08:00
Gabe Black	f63c260d89	ARM: Get rid of the Raddr operand.	2009-11-08 01:57:34 -08:00
Gabe Black	43e9209c21	ARM: Initialize processes in user mode. ... I accidentally left in a change to test using int registers in system mode. This change reverts that.	2009-11-08 00:54:32 -08:00
Gabe Black	a2b76516c4	ARM: Implement the shadow registers using register flattening.	2009-11-08 00:07:49 -08:00
Gabe Black	4a454c4f47	ARM: Set up an intregs.hh for ARM. ... Add constants for all the modes and registers, maps for aliasing, functions that use the maps and range check, and use a named constant instead of a magic number for the microcode register.	2009-11-08 00:07:35 -08:00
Gabe Black	18b21c1eca	ARM: Get rid of some unneeded register indexes.	2009-11-07 22:34:33 -08:00
Vince Weaver	5cf2e7ccf0	X86: Fix problem with movhps instruction ... This problem is like the one fixed with movhpd a few weeks ago. A +8 displacement is used to access memory when there should be none. This fix is needed for the perlbmk spec2k benchmark to run.	2009-11-04 13:22:15 -05:00
Nathan Binkert	2c5fe6f95e	build: fix compile problems pointed out by gcc 4.4	2009-11-04 16:57:01 -08:00
Vince Weaver	a1042db290	X86: Enable x86_64 vsyscall support ... 64-bit vsyscall is different than 32-bit. There are only two syscalls, time and gettimeofday. On a real system, there is complicated code that implements these without entering the kernel. That would be complicated to implement in m5. Instead we just place code that calls the regular syscalls (this is how tools such as valgrind handle this case). This is needed for the perlbmk spec2k benchmark.	2009-11-04 00:47:12 -05:00
Vince Weaver	9b0a747dd4	X86: Hook up time syscall on X86 ... This has been tested and verified that it works.	2009-11-04 00:19:15 -05:00
Vince Weaver	a12557439b	X86: Add support for x86 psrldq and pslldq instructions ... These are complicated instructions and the micro-code might be suboptimal. This has been tested with some small sample programs (attached) The psrldq instruction is needed by various spec2k programs.	2009-10-30 12:49:37 -04:00
Vince Weaver	5873ec2238	X86: Implement movd_Vo_Edp on X86 ... This patch implements the movd_Vo_Edp series of instructions. It addresses various concerns by Gabe Black about which file the instruction belonged in, as well as supporting REX prefixed instructions properly. This instruction is needed for some of the spec2k benchmarks, most notably bzip2.	2009-10-30 15:52:33 -04:00
Vince Weaver	b2067840a6	X86: Implement the X86 sse2 haddpd instruction ... This patch implements the haddpd instruction. It fixes the problem in the previous version (pointed out by Gabe Black) where an incorrect result would happen if you issue the instruction with the same argument twice, i.e. "haddpd %xmm0,%xmm0" This instruction is used by many spec2k benchmarks.	2009-10-30 14:19:06 -04:00
Vince Weaver	cf269025f9	X86: Hookup truncate/ftruncate syscalls on X86 ... This patch hooks up the truncate, ftruncate, truncate64 and ftruncate64 system calls on 32-bit and 64-bit X86. These have been tested on both architectures. ftruncate/ftruncate64 is needed for the f90 spec2k benchmarks.	2009-10-30 12:51:13 -04:00
Gabe Black	3f722b991f	Syscalls: Make system calls access arguments like a stack, not an array. ... When accessing arguments for a syscall, the position of an argument depends on the policies of the ISA, how much space preceding arguments took up, and the "alignment" of the index for this particular argument into the number of possible storate locations. This change adjusts getSyscallArg to take its index parameter by reference instead of value and to adjust it to point to the possible location of the next argument on the stack, basically just after the current one. This way, the rules for the new argument can be applied locally without knowing about other arguments since those have already been taken into account implicitly. All system calls have also been changed to reflect the new interface. In a number of cases this made the implementation clearer since it encourages arguments to be collected in one place in order and then used as necessary later, as opposed to scattering them throughout the function or using them in place in long expressions. It also discourages using getSyscallArg over and over to retrieve the same value when a temporary would do the job.	2009-10-30 00:44:55 -07:00
Gabe Black	f9624e49f6	X86: Replace "DISPLACEMENT" with disp in movhpd.	2009-10-27 23:50:25 -07:00
Vince Weaver	87b97f28bd	Fix problem with the x86 sse movhpd instruction. ... The movhpd instruction was writing to the wrong memory offset.	2009-10-27 14:11:06 -04:00
Vince Weaver	14691148cd	Implement X86 sse2 movdqu and movdqa instructions ... The movdqa instruction should enforce 16-byte alignment. This implementation does not do that. These instructions are needed for most of x86_64 spec2k to run.	2009-10-21 13:40:43 -04:00
Vince Weaver	5b6f707a00	hook up stat syscall on 64-bit x86_SE	2009-10-20 16:48:00 -04:00
Vince Weaver	2b473cb099	hook up stat64 syscall on 32-bit X86_SE	2009-10-20 14:44:51 -04:00
Vince Weaver	776f9405fa	Fix stat64 structure on 32-bit X86_SE ... The st_size entry was in the wrong place (see linux-2.6.29/arch/x86/include/asm/stat.h ) Also, the packed attribute is needed when compiling on a 64-bit machine, otherwise gcc adds extra padding that break the layout of the structure.	2009-10-20 15:15:37 -04:00
Timothy M. Jones	835a55e7f3	POWER: Add support for the Power ISA ... This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06.	2009-10-27 09:24:39 -07:00
Timothy M. Jones	1b2d75d6d2	syscall: Addition of an ioctl command code for Power.	2009-10-24 10:53:59 -07:00
Vince Weaver	56154cff5e	Enable getuid and getgid related syscalls on X86_SE ... I've tested these on x86 and they work as expected. In theory for 32-bit x86 we should have some sort of special handling for the legacy 16-bit uid/gid syscalls, but in practice modern toolchains don't use the 16-bit versions, and m5 sets the uid and gid values to be less than 16-bits anyway. This fix is needed for the perl spec2k benchmarks to run.	2009-10-19 17:29:34 -04:00
Vince Weaver	22dc2b5595	Ignore rt_sigaction() syscalls on x86 and x86_64 ... This is currently how alpha handles this syscall. This is needed for the gcc spec2k benchmarks to run.	2009-10-16 13:54:20 -04:00
Gabe Black	010b13c937	ISA: Fix compilation.	2009-10-17 01:13:41 -07:00
Vince Weaver	30a185dcd0	Hook up the munmap() syscall for 32-bit x86. ... This is straightforward, as munmapFunc() doesn't do anything. I've tested it with code running munmap() just in case.	2009-10-10 22:31:56 -07:00
Gabe Black	44ceb80c2d	X86: Make successive anonymous mmaps move down in 32 bit SE mode Linux.	2009-10-02 01:32:58 -07:00
Nathan Binkert	baca1f0566	isa_parser: Turn the ISA Parser into a subclass of Grammar. ... This is to prepare for future cleanup where we allow SCons to create a separate grammar class for each ISA	2009-09-23 18:28:29 -07:00
Nathan Binkert	d9f39c8ce7	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	2009-09-23 08:34:21 -07:00
Nathan Binkert	e9288b2cd3	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
Nathan Binkert	9a8cb7db7e	python: Move more code into m5.util allow SCons to use that code. ... Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. --HG-- rename : src/python/m5/convert.py => src/python/m5/util/convert.py rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py	2009-09-22 15:24:16 -07:00
Korey Sewell	b7094ec38b	mips: fix command line arguments ... arguments were not being saved correctly into M5 memory	2009-09-17 15:59:43 -04:00
Gabe Black	931405da2f	X86: Fix the expected size of the immediate offset in MOV_MI.	2009-09-17 02:56:06 -07:00
Gabe Black	c876a781a5	X86: Sign extend the immediate of wripi like the register version.	2009-09-16 19:29:51 -07:00
Gabe Black	7a0ef6c36f	X86: Make the imm8 member of immediate microops really 8 bits consistently.	2009-09-16 19:28:57 -07:00
Gabe Black	239f1dea31	X86: Fix checking the NT bit during an IRET.	2009-09-16 19:28:30 -07:00
Gabe Black	eec6bfaa9d	X86: Fix setting the busy bit in the task descriptor in LTR.	2009-09-16 19:28:01 -07:00
Vince Weaver	9b8e61beb3	Syscalls: Implement sysinfo() syscall.	2009-09-15 22:36:47 -07:00
Vince Weaver	0f569b4d9d	SPARC: Make resTemp in udivcc wide enough to hold all the bits we need.	2009-09-15 05:48:20 -07:00
Vince Weaver	9900ac95b5	[mq]: x86syscalls.patch	2009-09-15 05:30:08 -07:00
Gabe Black	e251b42c59	Merge with head.	2009-08-23 14:19:14 -07:00
Gabe Black	d0d597004f	X86: Preserve the NO_ACCESS flag when giving CDA a specialized interface.	2009-08-23 14:16:58 -07:00
Nathan Binkert	890be77362	X86: fix some simple compile issues ... static should not be used for constants that are not inside a class definition.	2009-08-21 09:10:25 -07:00
Gabe Black	e8c0ca5cd1	X86: Fix the decoding for and fill out FST and FSTP.	2009-08-20 00:42:14 -07:00
Gabe Black	843d064668	X86: Add microassembler symbols for floating point stack register operands.	2009-08-20 00:41:27 -07:00
Gabe Black	ed088ed15e	X86: Decode the immediate byte opcode extension for 3dNow! instructions.	2009-08-18 00:52:47 -07:00
Gabe Black	fd45c04cad	X86: Decode three byte opcodes.	2009-08-18 00:52:45 -07:00
Gabe Black	9df74ab401	X86: Double check the two byte portion of the decoder and fix bugs/clean up.	2009-08-17 20:25:15 -07:00
Gabe Black	92867cac95	X86: Implement MOVNTI.	2009-08-17 20:25:15 -07:00
Gabe Black	6415252a0f	X86: Initialize the MXCSR in SE mode.	2009-08-17 20:25:14 -07:00
Gabe Black	56d87cdc08	X86: Implement MOVQ2DQ.	2009-08-17 20:25:14 -07:00
Gabe Black	317a9ac6d1	X86: Implement MOVDQ2Q.	2009-08-17 20:25:14 -07:00
Gabe Black	1606663aa9	X86: Implement the media instructions that convert fp values to ints.	2009-08-17 20:25:14 -07:00
Gabe Black	e3ef432a55	X86: Implement a microop for converting fp values to ints.	2009-08-17 20:25:14 -07:00
Gabe Black	123ea3b229	X86: Implement the instructions that compare fp values and write a mask as a result.	2009-08-17 20:25:14 -07:00
Gabe Black	288f428632	X86: Implement a microop that compares fp values and writes a mask as a result.	2009-08-17 20:25:14 -07:00
Gabe Black	87ad677209	X86: Implement the instructions that compare fp values and write to rflags.	2009-08-17 20:25:14 -07:00
Gabe Black	2c9ee52c37	X86: Implement a microop that compares fp values and writes to rflags.	2009-08-17 20:25:14 -07:00
Gabe Black	7d4db7266e	X86: Implement MOVSS.	2009-08-17 20:25:14 -07:00
Gabe Black	179fd4e536	X86: Implement LDMXCSR.	2009-08-17 20:25:14 -07:00
Gabe Black	b315c3effc	X86: Implement STMXCSR.	2009-08-17 20:25:13 -07:00
Gabe Black	7fbd9e1296	X86: Implement the shuffle media instructions.	2009-08-17 20:25:13 -07:00
Gabe Black	1fed0161d9	X86: Implement a shuffle media microop.	2009-08-17 20:25:13 -07:00
Gabe Black	d9970f139a	X86: Implement the mask move instructions.	2009-08-17 20:22:56 -07:00
Gabe Black	75528a497c	X86: Implement a mask move microop.	2009-08-17 20:22:56 -07:00
Gabe Black	90dc1abd0b	X86: Implement the instructions that move sign bits.	2009-08-17 20:22:56 -07:00
Gabe Black	90786e43fc	X86: Implement a microop that moves sign bits.	2009-08-17 20:22:56 -07:00
Gabe Black	4c23e631f2	X86: Implement the insert/extract instructions.	2009-08-17 20:22:56 -07:00
Gabe Black	c0e850c77a	X86: Fix a bug in the decoder where the insert/extract instructions go.	2009-08-17 20:22:56 -07:00
Gabe Black	965e546df3	X86: Extend mov2int and mov2fp so they can support insert and extract instructions.	2009-08-17 20:22:56 -07:00
Gabe Black	2beab367d7	X86: Implement the media average instructions.	2009-08-17 20:15:16 -07:00
Gabe Black	f6b12bfa8d	X86: Implement a media average microop.	2009-08-17 20:15:16 -07:00
Gabe Black	45bae0c70f	X86: Implement the multiply and add instructions.	2009-08-17 20:15:16 -07:00
Gabe Black	200fed31de	X86: Let the integer multiply microop use every other possible source value.	2009-08-17 20:15:16 -07:00
Gabe Black	cf2fc2613d	X86: Implement the media shifts that operate on 64 bits or less at a time.	2009-08-17 20:15:16 -07:00
Gabe Black	c8a0cf5df7	X86: Implement the media shift microops. These don't handle full 128 bit wide shifts.	2009-08-17 20:15:16 -07:00
Gabe Black	dabbc7d9d3	X86: Implement the sum of absolute differences instructions.	2009-08-17 20:15:16 -07:00
Gabe Black	470dcef229	X86: Implement a "sum of absolute differences" microop.	2009-08-17 20:15:16 -07:00
Gabe Black	31d29ee3f8	X86: Implement the media integer subtract instructions.	2009-08-17 20:15:15 -07:00
Gabe Black	a4437f8f14	X86: Implement an integer media subtract microop.	2009-08-17 20:15:15 -07:00
Gabe Black	c40698e315	X86: Implement the integer media multiply instructions.	2009-08-17 20:15:15 -07:00
Gabe Black	3424de2861	X86: Implement a media integer multiply microop.	2009-08-17 20:15:15 -07:00
Gabe Black	c76459e5a7	X86: Make larger blocks of instructions use the Inst format by default.	2009-08-17 20:04:03 -07:00
Gabe Black	5d834c28eb	X86: Implement the integer media max instructions.	2009-08-17 20:04:03 -07:00
Gabe Black	c9a954c77a	X86: Implement an integer media max microop.	2009-08-17 20:04:03 -07:00
Gabe Black	be6267e895	X86: Implement the integer media min instructions.	2009-08-17 20:04:03 -07:00
Gabe Black	e2759fe69c	X86: Add a media integer min microop.	2009-08-17 20:04:02 -07:00
Gabe Black	e678df6263	X86: Implement the media integer addition instructions.	2009-08-17 20:04:02 -07:00
Gabe Black	c278760da0	X86: Implement an integer media addition microop with optional saturation.	2009-08-17 20:04:02 -07:00
Gabe Black	f5ac4f51d9	X86: Implement the instructions that convert between forms of floating point.	2009-08-17 20:04:02 -07:00
Gabe Black	83df309a7e	X86: Implement a media microop that converts between floating point data types.	2009-08-17 20:04:02 -07:00
Gabe Black	35b0983ca9	X86: Implement the instructions that compare fp values and write masks as the result.	2009-08-17 20:04:02 -07:00
Gabe Black	f122c93faa	X86: Implement a microop that compares fp values and writes a mask as its result.	2009-08-17 20:04:02 -07:00
Gabe Black	df1b3fdcfb	X86: Implement the MOVDDUP instruction.	2009-08-17 18:50:29 -07:00
Gabe Black	cf9634a43f	X86: Implement many of the media mov instructions.	2009-08-17 18:44:44 -07:00
Gabe Black	ae64377afe	X86: Implement the media instructions that convert integer values to floating point.	2009-08-17 18:41:27 -07:00
Gabe Black	8e97cd9c8f	X86: Implement a media microop for converting integer values to floating point.	2009-08-17 18:41:25 -07:00
Gabe Black	b34b507fd8	X86: Implement the floating point media instructions.	2009-08-17 18:40:40 -07:00
Gabe Black	af3a53726b	X86: Implement a floating point media divide microop.	2009-08-17 18:40:38 -07:00
Gabe Black	fcb5b2226c	X86: Implement the floating point media multiply instructions.	2009-08-17 18:38:53 -07:00
Gabe Black	94e771e283	X86: Implement a floating point media multiply microop.	2009-08-17 18:38:51 -07:00
Gabe Black	dd81a34829	X86: Implement the floating point media subtract instructions.	2009-08-17 18:36:20 -07:00
Gabe Black	9fee8b75aa	X86: Implement a media floating point subtract microop.	2009-08-17 18:36:18 -07:00
Gabe Black	49c2610c04	X86: Implement the floating point media add instructions.	2009-08-17 18:35:06 -07:00
Gabe Black	df163284fc	X86: Implement a floating point media add microop.	2009-08-17 18:35:04 -07:00
Gabe Black	449db8a370	X86: Implement the media sqrt instructions.	2009-08-17 18:34:19 -07:00
Gabe Black	6a923c1c79	X86: Implement a media square root microop.	2009-08-17 18:34:16 -07:00
Gabe Black	09eed9ff62	X86: Implement the media floating point max instructions.	2009-08-17 18:33:28 -07:00
Gabe Black	8d37ce8652	X86: Implement the floating point media max microop.	2009-08-17 18:33:25 -07:00
Gabe Black	34f528bd95	X86: Implement the media floating point min instructions.	2009-08-17 18:32:12 -07:00
Gabe Black	1d706c0434	X86: Implement a floating point media min microop.	2009-08-17 18:32:09 -07:00
Gabe Black	e20c8a4b05	X86: Implement the pack instructions.	2009-08-17 18:32:08 -07:00
Gabe Black	1273277d3b	X86: Create a pack media microop.	2009-08-17 18:27:54 -07:00
Gabe Black	e6b5192c26	X86: Rename sel to ext for media microops.	2009-08-17 18:27:44 -07:00
Gabe Black	80b4456fec	X86: Move the MMX version of MOVD into the simd64 directory.	2009-08-17 18:27:30 -07:00
Gabe Black	63403bd562	X86: Implement the remaining unpack instructions.	2009-08-17 18:27:19 -07:00
Gabe Black	7b18f8a062	X86: Implement PANDN, ANDNPS, and ANDNPD.	2009-08-17 18:25:00 -07:00
Gabe Black	458521f055	X86: Implement a multimedia andn microop.	2009-08-17 18:24:58 -07:00
Gabe Black	3633392ec4	X86: Implement PAND, ANDPS, and ANDPD.	2009-08-17 18:24:18 -07:00
Gabe Black	ab49a34a4e	X86: Implement a multimedia and microop.	2009-08-17 18:24:16 -07:00
Gabe Black	83a78072df	X86: Implement POR, ORPD and ORPS.	2009-08-17 18:23:33 -07:00
Gabe Black	25c6b016a6	X86: Implement a media or microop.	2009-08-17 18:23:30 -07:00
Gabe Black	f9346d25c8	X86: Implement PXOR.	2009-08-17 18:23:04 -07:00
Gabe Black	69f0bf743c	X86: (Re)implement XORPS and XORPD.	2009-08-17 18:22:37 -07:00
Gabe Black	982b3ad1f0	X86: Implement a media xor microop.	2009-08-17 18:22:33 -07:00
Gabe Black	f3fb444af4	X86: Implement PUNPCKLQDQ.	2009-08-17 18:21:46 -07:00
Gabe Black	cfaeb5eaf7	X86: Implement PUNPCKHQDQ.	2009-08-17 18:21:09 -07:00
Gabe Black	aabbb22cca	X86: Implement PUNPCKHDQ.	2009-08-17 18:20:50 -07:00
Gabe Black	535ba241f8	X86: Implement PUNPCKHWD.	2009-08-17 18:19:43 -07:00
Gabe Black	093b5b3274	X86: Implement PUNPCKHBW.	2009-08-17 18:19:19 -07:00
Gabe Black	3ae2f03927	X86: Implement PUNPCKLDQ.	2009-08-17 18:19:01 -07:00
Gabe Black	673b19f5d4	X86: Implement PUNPCKLWD.	2009-08-17 18:18:40 -07:00
Gabe Black	ae4ee21ecd	X86: Implement the versions of PUNPCKLBW that use XMM registers.	2009-08-17 18:18:19 -07:00
Gabe Black	24496060e5	X86: Implement the MOVQ instruction.	2009-08-17 18:17:29 -07:00
Gabe Black	f1bfa9d6e4	X86: Implement the lfpimm microop.	2009-08-17 18:17:26 -07:00
Gabe Black	fca7cb83f0	X86: Implement the versions of MOVD that have an MMX source.	2009-08-17 18:16:07 -07:00
Gabe Black	247ed2379d	X86: Implement the versions of PUNPCKLBW that use MMX registers.	2009-08-17 18:15:42 -07:00
Gabe Black	ecc62e750e	X86: Implement an unpack microop.	2009-08-17 18:15:39 -07:00
Gabe Black	6457fb7003	X86: Implement the versions of MOVD that have an MMX destination.	2009-08-17 18:15:24 -07:00
Gabe Black	191590bcc4	X86: Ignore the size part of XMM/MMX operands. The instructions know what they want.	2009-08-17 18:15:23 -07:00
Gabe Black	33cb4c2f09	X86: Use suffixes to differentiate XMM/MMX/GPR operands.	2009-08-17 18:15:21 -07:00
Gabe Black	3a4438a868	X86: Add microcode assembler symbols for mmx registers.	2009-08-17 18:15:19 -07:00
Gabe Black	2f1001e95c	X86: Set up a media microop framework and create mov2int and mov2fp microops.	2009-08-17 18:15:18 -07:00
Gabe Black	cec4e3b39e	X86: Create base classes for use with media/SIMD microops.	2009-08-17 18:15:16 -07:00
Gabe Black	0b68fbdbe1	X86: Turn the DIV and IDIV microcode into templates and generate all the variants.	2009-08-17 18:15:14 -07:00
Gabe Black	a9b2bf5119	X86: Remove some FIXMEs from IDIV that have been fixed.	2009-08-17 18:15:13 -07:00
Gabe Black	3f2f3bede8	X86: Turn the CMPXCHG8B microcode into a template and generate each variant.	2009-08-17 18:15:00 -07:00
Gabe Black	32c8514b45	X86: Fix a bug introduced to IDIV in a recent attempt to fix another bug.	2009-08-17 00:20:03 -07:00
Gabe Black	c5fae51774	X86: Implement the CMPXCHG8B/CMPXCHG16B instruction.	2009-08-09 01:01:41 -07:00
Gabe Black	bbf117b20e	X86: Don't clobber the original dividend when doing signed divide.	2009-08-09 01:01:18 -07:00
Gabe Black	3b07a5829d	X86: Decode byte sized singed divide as byte sized.	2009-08-09 01:00:47 -07:00
Gabe Black	6e97feb8a5	X86: Make not taken conditional moves leave the destination alone. Adjust CMOVcc. ... The manuals from both AMD and Intel say that when writing to a 32 bit destination in 64 bit mode, the upper 32 bits of the register are filled with zeros. They also both say that the CMOV instructions leave their destination alone when their condition fails. Unfortunately, it seems that CMOV will zero extend its destination register whether or not it was supposed to actually do a move on both platforms. This seems to be the only case where this happens, but it would be hard to say for sure.	2009-08-08 17:23:19 -07:00
Gabe Black	7c606e3835	X86: (Re)Implemented SHRD.	2009-08-07 10:13:33 -07:00
Gabe Black	4f5270f946	X86: Implement SHLD.	2009-08-07 10:13:24 -07:00
Gabe Black	3a55fc5cac	X86: Implement shift right/left double microops. ... This is my best guess as far as what these should do. Other existing microops use implicit registers, mul1s and mul1u for instance, so this should be ok. The microop that loads the implicit DoubleBits register would fall into one of the microop slots for moving to/from special registers.	2009-08-07 10:13:20 -07:00
Gabe Black	62a2e85c9a	X86: Make the qaud width bswap instruction handle the fact that 32 bit operations zero extend.	2009-08-07 10:12:58 -07:00
Gabe Black	0526f453aa	X86: Use the right field when using legacy prefixes to distinguish instructions.	2009-08-07 10:12:52 -07:00
Gabe Black	2daba26359	X86: Don't truncate the immediate parameter for the ENTER instruction.	2009-08-07 10:12:29 -07:00
Gabe Black	2e3446a410	X86: Adjust the various sizes used for the enter and leave instructions.	2009-08-06 21:44:42 -07:00
Gabe Black	c7b894a06f	X86: Make scas compare its operands in the right order.	2009-08-06 21:44:41 -07:00
Gabe Black	011c1865ad	X86: Fix a copy/paste error for cmovnp.	2009-08-06 21:44:40 -07:00
Gabe Black	da2df2fc25	X86: Make conditional moves zero extend their 32 bit destinations always.	2009-08-05 03:07:55 -07:00
Gabe Black	b64d0bdeda	X86: Fix condition code setting for signed multiplies with negative results.	2009-08-05 03:07:01 -07:00
Gabe Black	2914a8eb16	X86: Make the check for negative operands for sign multiply more direct.	2009-08-05 03:06:37 -07:00
Gabe Black	e2e0ae576a	X86: Make sure immediate values are truncated properly. ... Register values will be "picked" which will assure they don't have junk beyond the part we're using. Immediate values don't go through a similar process, so we should truncate them explicitly.	2009-08-05 03:06:01 -07:00
Gabe Black	ef3896d851	X86: Use the new forced folding mechanism for the SAHF and LAHF instructions.	2009-08-05 03:04:17 -07:00
Gabe Black	664d50b439	X86: Fix the indexing for ah in byte division instructions.	2009-08-05 03:03:41 -07:00
Gabe Black	abe8fb3844	X86: Fix the indexing for ah in byte multiply instructions.	2009-08-05 03:03:28 -07:00
Gabe Black	df1abc4412	X86: Let microops force folding an index into the high byte of a register.	2009-08-05 03:03:07 -07:00
Gabe Black	c4140d7d60	X86: Handle rotate left with carry instructions that go all the way around or more.	2009-08-05 03:02:28 -07:00
Gabe Black	3990445354	X86: Set the flags on rotate left with carry instructions.	2009-08-05 03:02:05 -07:00
Gabe Black	d265f7683e	X86: Handle rotate right with carry instructions that go all the way around or more.	2009-08-05 03:01:49 -07:00
Gabe Black	77dc6b33ee	X86: Fix the overflow bit for rotate right with carry.	2009-08-05 03:01:23 -07:00
Gabe Black	c8b1a4583e	X86: Fix the computation of the bottom part of rotate right with carry.	2009-08-05 03:01:07 -07:00
Gabe Black	bab4597fc5	X86: Fix the computation of the upper part of rotate right with carry.	2009-08-05 03:00:43 -07:00
Gabe Black	4e4adcaaa8	X86: Set the flags for rotate right with carry instructions.	2009-08-05 03:00:23 -07:00
Gabe Black	64d7948692	X86: Handle rotating right all the way around or more.	2009-08-05 03:00:03 -07:00
Gabe Black	88041f75c4	X86: Set the flags on a rotate right instruction.	2009-08-05 02:59:39 -07:00
Gabe Black	029d360db2	X86: Make shifts/rotations that write to 32 bits of a register zero extend.	2009-08-05 02:59:25 -07:00
Gabe Black	7f9a3af250	X86: Handle left rotations that go all the way around or more.	2009-08-05 02:58:54 -07:00
Gabe Black	99adfd9dae	X86: Actually set the flags on a rotate left instruction.	2009-08-05 02:58:20 -07:00
Gabe Black	c087b60af3	X86: Fix the sar carry flag.	2009-08-05 02:58:03 -07:00
Gabe Black	860f0f8350	X86: Fix sign extension when doing an arithmetic shift right by 0.	2009-08-05 02:57:47 -07:00
Gabe Black	a238959c34	X86: Fix the carry flag for shr.	2009-08-05 02:56:49 -07:00
Gabe Black	22a5f66820	X86: Fix the carry flag for shl.	2009-08-05 02:56:38 -07:00
Gabe Black	df2c862a07	X86: Fix how the parity flag is computed. ... It's only for the lowest order byte, and I had the polarity wrong.	2009-08-05 02:56:12 -07:00
Gabe Black	676dc6d292	X86: Fix segment override prefixes on instructions that use rbp/rsp and a displacement.	2009-08-03 11:01:40 -07:00
Gabe Black	aff57202b4	X86: Fix the high result of mul1s, and removed undefined shifts from the mult microops.	2009-08-02 08:39:29 -07:00
Steve Reinhardt	1c28004654	Clean up some inconsistencies with Request flags.	2009-08-01 22:50:13 -07:00
Korey Sewell	aa75b9a7a7	merge mips fix and statetrace changes	2009-07-31 10:40:42 -04:00
Korey Sewell	60063cc700	mips: fix ll/sc pairs working incorrectly because of accidental clobber of LLFLAG	2009-07-31 09:34:29 -04:00
Nathan Binkert	3dd3de5feb	compile: fix accidental conversion of == into =	2009-07-30 17:42:57 -07:00
Gabe Black	4971331b4f	ARM: Mul and mla ignore the c and v flags, but we were setting them to 1.	2009-07-29 22:24:00 -07:00
Gabe Black	b066e717f4	ARM: Fix an instruction in the cmpxchg kernel provided routine. ... The instruction was encoded as a load instead of the intended store.	2009-07-29 00:18:26 -07:00
Gabe Black	c2da5bae17	ARM: Get rid of a stray line in the set_tls handler.	2009-07-29 00:17:20 -07:00
Gabe Black	1e04b6281d	ARM: Make the ARM native tracer stop M5 if control diverges. ... If the control flow of M5's executable and statetrace's target process get out of sync even a little, there will be a LOT of output, very little of which will be useful. There's also almost no hope for recovery. In those cases, we might as well give up and not generate a huge, mostly worthless trace file.	2009-07-29 00:17:11 -07:00
Gabe Black	873112ea99	ARM: Make sure the target process doesn't run away from statetrace.	2009-07-29 00:14:43 -07:00
Ali Saidi	0a9eb59e6f	ARM: Ignore the "times" system call.	2009-07-29 00:09:46 -07:00
Ali Saidi	19a4fb0ff3	ARM: Fix an ioctl constant.	2009-07-29 00:09:44 -07:00
Ali Saidi	daf8718da9	ARM: Update some syscall constants and delete others that are Alpha only.	2009-07-27 00:54:55 -07:00
Gabe Black	d3f2992e39	ARM: Decode fstmx and fldmx instructions. We can ignore them for now.	2009-07-27 00:54:50 -07:00
Gabe Black	52b4a7c36f	ARM: Only send information that changed between statetrace and M5.	2009-07-27 00:54:30 -07:00
Gabe Black	90d3d3535b	imported patch nativetracestreamline.patch	2009-07-27 00:54:24 -07:00
Gabe Black	8ec235c7b1	ARM: Make native trace print out what instruction caused an error.	2009-07-27 00:54:09 -07:00
Gabe Black	c18d6cb1a7	ARM: Implement a basic version of the fmxr instruction.	2009-07-27 00:53:29 -07:00
Gabe Black	2828fa459d	ARM: Implement a basic version of the fmrx instruction.	2009-07-27 00:53:24 -07:00
Gabe Black	4079792f2b	ARM: Add in spots for the VFP control registers.	2009-07-27 00:53:10 -07:00
Gabe Black	b560acfe17	ARM: Fix the CLZ instruction.	2009-07-27 00:52:59 -07:00
Gabe Black	dc0df3f396	ARM: Initialize the CPSR so that we're in user mode.	2009-07-27 00:52:48 -07:00
Gabe Black	b8bf34be05	ARM: Set up the initial stack frame to match a recent Linux.	2009-07-27 00:52:31 -07:00
Gabe Black	a41e132007	ARM: Make native trace only print when registers are changing value. ... When registers have incorrect values but aren't actively changing, it's likely they're not being modified at all. The fact that they're still wrong isn't very important.	2009-07-27 00:52:01 -07:00
Gabe Black	519ace4dfd	ARM: Add a native tracer. ... --HG-- rename : src/arch/sparc/SparcNativeTrace.py => src/arch/arm/ArmNativeTrace.py rename : src/arch/sparc/nativetrace.cc => src/arch/arm/nativetrace.cc rename : src/arch/sparc/nativetrace.hh => src/arch/arm/nativetrace.hh	2009-07-27 00:51:35 -07:00
Ali Saidi	e7640227ca	ARM: Fix fstat/fstat64 structs to match EABI definitions.	2009-07-27 00:51:20 -07:00
Ali Saidi	99831ed938	ARM: Handle register indexed system calls.	2009-07-27 00:51:01 -07:00
Gabe Black	ef4e8b04a6	SPARC: Fix a minor compile bug in native trace on gcc > 4.1.	2009-07-25 15:14:00 -07:00
Gabe Black	9ba2ed8532	MIPS: Small fix I forgot to qrefresh into my last change.	2009-07-22 01:57:55 -07:00
Gabe Black	7f0c07bf03	MIPS: Style/formatting sweep of the decoder itself.	2009-07-22 01:51:10 -07:00
Gabe Black	c874bfae3f	MIPS: Format the register index constants like the other ISAs. ... Also a few more style fixes.	2009-07-21 23:38:26 -07:00
Gabe Black	74584d79b6	MIPS: Get MIPS_FS to compile, more style fixes. ... Some breakage was from my BitUnion change, some was much older.	2009-07-21 01:09:05 -07:00
Gabe Black	7548082d3b	MIPS: Many style fixes. ... White space, commented out code, some other minor fixes.	2009-07-21 01:08:53 -07:00
Gabe Black	dc0a017ed0	isa_parser: Get rid of the now unused ControlBitfieldOperand.	2009-07-20 20:20:17 -07:00
Gabe Black	5161bc19d9	MIPS: Use BitUnions instead of bits() functions and constants. ... Also fix style issues in regions around these changes.	2009-07-20 20:14:15 -07:00
Gabe Black	3e8e813218	CPU: Separate out native trace into ISA (in)dependent code and SimObjects. ... --HG-- rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py	2009-07-19 23:54:56 -07:00
Gabe Black	f0cb698a87	X86: Move a displaced comment back to where it goes.	2009-07-19 23:51:47 -07:00
Gabe Black	563654275f	X86: Add some misc registers for FP control state.	2009-07-19 23:51:41 -07:00
Gabe Black	d85cd08113	X86: Set up a named constant for the "fold bit" for int register indices.	2009-07-17 18:49:22 -07:00
Gabe Black	7b6587fc9c	X86: Tame the wilds of def operands.	2009-07-17 00:29:56 -07:00
Gabe Black	df378285f8	X86: Shift some register flattening work into the decoder.	2009-07-17 00:29:42 -07:00
Gabe Black	e9eccf7225	X86: Add range checks for miscreg indexing utility functions.	2009-07-16 09:30:14 -07:00
Gabe Black	ba6b8389ee	X86: Take limitted advantage of the compilers type checking for microop operands.	2009-07-16 09:29:29 -07:00
Gabe Black	80c834ccac	X86: Fix a number of places where the wrong form of a microop was used.	2009-07-16 09:27:56 -07:00
Gabe Black	3f9b0cc5ca	X86: Fix x87 stack register indexing.	2009-07-16 09:26:38 -07:00
Jack Whitham	fce4412d76	ARM: Fix the "open" flag constants.	2009-07-14 21:03:33 -07:00
Gabe Black	60577eb4ca	ISAs: Get rid of the IControl operand type. ... A separate operand type is not necessary to use two bitfields to generate the index.	2009-07-10 01:21:04 -07:00
Gabe Black	64fe7af51a	SPARC: Set up a lookup table for integer register flattening. ... Using a look up table changed the run time of the SPARC_FS solaris boot regression from: real 14m45.951s user 13m57.528s sys 0m3.452s to: real 12m19.777s user 12m2.685s sys 0m2.420s	2009-07-10 01:01:47 -07:00
Gabe Black	9993ca8280	X86: Fold the MiscRegFile all the way into the ISA object.	2009-07-09 20:29:02 -07:00
Gabe Black	60d47aa5f9	SPARC: Fold the MiscRegFile all the way into the ISA object.	2009-07-09 20:28:50 -07:00
Gabe Black	de7f462219	MIPS: Fold the MiscRegFile all the way into the ISA object.	2009-07-09 20:28:39 -07:00
Gabe Black	e14c408b62	ARM: Fold the MiscRegFile all the way into the ISA object.	2009-07-09 20:28:27 -07:00
Gabe Black	5643a222e3	Alpha: Missed a file in an earlier changeset.	2009-07-09 00:20:41 -07:00
Gabe Black	c9a27d85b9	Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.	2009-07-08 23:02:22 -07:00
Gabe Black	3d39b62132	Alpha: Pull the MiscRegFile fully into the ISA object.	2009-07-08 23:02:22 -07:00
Gabe Black	b398b8ff1b	Registers: Add a registers.hh file as an ISA switched header. ... This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. --HG-- rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh	2009-07-08 23:02:21 -07:00
Gabe Black	997f36c711	Registers: Collapse ARM and MIPS regfile directories. ... --HG-- rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh	2009-07-08 23:02:21 -07:00
Gabe Black	aa031e1c11	Alpha: Move reg_redir into its own files, and move some constants into regfile.hh.	2009-07-08 23:02:21 -07:00
Gabe Black	5c37d10624	Registers: Eliminate the ISA defined RegFile class.	2009-07-08 23:02:21 -07:00
Gabe Black	9bf22992ee	Alpha: Get rid of function prototypes with no implementations.	2009-07-08 23:02:21 -07:00
Gabe Black	43345bff6c	Registers: Move the PCs out of the ISAs and into the CPUs.	2009-07-08 23:02:21 -07:00
Gabe Black	1b29f1621d	ARM, Simple CPU: Fix an index and add assert checks.	2009-07-08 23:02:21 -07:00
Gabe Black	0338c83c9d	MIPS: Get rid of an orphaned MIPS .cc file.	2009-07-08 23:02:21 -07:00
Gabe Black	6ebce9d65a	Alpha: Phase out Alpha's intregfile.hh and intregfile.cc.	2009-07-08 23:02:21 -07:00
Gabe Black	faa6ebebe1	SPARC: Phase out SPARC's intregfile.hh.	2009-07-08 23:02:20 -07:00
Gabe Black	ecde884404	X86: Phase out x86's intregfile.hh.	2009-07-08 23:02:20 -07:00
Gabe Black	301df68c73	MIPS: Phase out MIPS's int_regfile.hh.	2009-07-08 23:02:20 -07:00
Gabe Black	27b6148f47	ARM: Flush out the ARM's int_regfile.hh.	2009-07-08 23:02:20 -07:00
Gabe Black	a480ba00b9	Registers: Eliminate the ISA defined integer register file.	2009-07-08 23:02:20 -07:00
Gabe Black	0cb180ea0d	Registers: Eliminate the ISA defined floating point register file.	2009-07-08 23:02:20 -07:00
Gabe Black	25884a8773	Registers: Get rid of the float register width parameter.	2009-07-08 23:02:20 -07:00
Gabe Black	32daf6fc3f	Registers: Add an ISA object which replaces the MiscRegFile. ... This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.	2009-07-08 23:02:20 -07:00
Gabe Black	3e2cad8370	ARM: Use custom read/write code to alias R15 with the PC.	2009-07-08 23:02:20 -07:00
Gabe Black	b8b7c7314a	ISA parser: Allow alternative read/write code for operands.	2009-07-08 23:02:19 -07:00
Gabe Black	95392d3fb8	ARM: Move the remaining microops out of the decoder and into the ISA desc.	2009-07-08 23:02:19 -07:00
Gabe Black	1d4f338b39	ARM: Move the memory microops out of the decoder and into the ISA desc.	2009-07-08 23:02:19 -07:00
Gabe Black	70a75ceb84	ARM: Move the integer microops out of the decoder and into the ISA desc.	2009-07-08 23:02:19 -07:00
Gabe Black	4eb18cc07a	ARM: Improve memory instruction disassembly.	2009-07-08 23:02:19 -07:00
Gabe Black	2fb8d481ab	ARM: Tune up predicated instruction decoding.	2009-07-08 23:02:19 -07:00
Gabe Black	ddcf084f16	ARM: Get rid of the MemAcc and EAComp static insts.	2009-07-08 23:02:19 -07:00
Gabe Black	cae870eded	ARM: Get rid of end_addr in the ArmMacroStore constructor.	2009-07-08 23:02:19 -07:00
Gabe Black	311f77f33d	ARM: Add an AddrMode2 format for memory instructions that use address mode 2.	2009-07-08 23:02:19 -07:00
Gabe Black	826a3582ea	ARM: Don't always update CPSR.	2009-07-08 23:02:19 -07:00
Gabe Black	17f0943398	ARM: Add an AddrMode3 format for memory instructions that use address mode 3.	2009-07-08 23:02:19 -07:00
Gabe Black	dac0cb5c7e	ARM: Add load/store double instructions.	2009-07-08 23:02:10 -07:00
Gabe Black	1ca0688c4c	ARM: Add operands for the load/store double instructions.	2009-07-08 23:02:01 -07:00
Gabe Black	d029110fa1	X86: Fix a bug in IRET_PROT's microcode. The immediate form of sra was intended.	2009-07-08 23:01:54 -07:00
Gabe Black	240e214236	SPARC: Fix the parenthesis in inUserMode.	2009-07-05 16:07:09 -07:00
Jack Whitham	a223a065e6	ARM: Fix how address mode bits are handled.	2009-07-02 23:23:06 -07:00
Jack Whitham	a738006397	ARM: Fix the code snippet for mla.	2009-07-02 23:22:58 -07:00
Gabe Black	26c70ce2cb	ARM: Make DataOps select from a set of ways to set the c and v flags.	2009-07-01 22:17:06 -07:00
Gabe Black	148c265cf3	ARM: Get rid of some bitfields that aren't used. A few may need to be readded.	2009-07-01 22:16:51 -07:00
Gabe Black	7172e26cc4	ARM: Add a findLsbSet function and use it to implement clz.	2009-07-01 22:16:36 -07:00
Gabe Black	f5141c23fd	ARM: Add defaults for DataOp flag code.	2009-07-01 22:16:19 -07:00
Gabe Black	22a1ac22f4	ARM: Get rid of the val2 variable.	2009-07-01 22:16:05 -07:00
Gabe Black	ce9cb1ecb5	ARM: Centralize the declaration of resTemp.	2009-07-01 22:15:39 -07:00
Gabe Black	776a06fd39	ARM: Add a DataImmOp format similar to DataOp.	2009-07-01 22:12:10 -07:00
Gabe Black	4f98171479	ARM: Decode some media instructions. These are untested.	2009-07-01 22:11:54 -07:00
Gabe Black	b8f064c88c	ARM: Use the new DataOp format to simplify the decoder.	2009-07-01 22:11:39 -07:00
Gabe Black	f409d7819d	ARM: Add in some new artificial fields that make decoding a little easier.	2009-07-01 22:11:27 -07:00
Gabe Black	1f0c0a6688	ARM: Recognize the IntRegs trace flag.	2009-07-01 22:11:12 -07:00
Gabe Black	065cb59427	ARM: Add a DataOp format so data op definitions can be aggregated.	2009-07-01 22:10:58 -07:00
Gabe Black	1ea14b8fac	ARM: Show more information when disassembling data processing intstructions. ... This will need more work, but it should be a lot closer.	2009-06-27 00:30:23 -07:00
Gabe Black	56f1845471	ARM: Show branch targets relative to the nearest symbol.	2009-06-27 00:29:30 -07:00
Gabe Black	a4ac3fad7a	ARM: Write a function for printing mnemonics and predicates.	2009-06-27 00:29:12 -07:00
Gabe Black	38d8bc64ba	ARM: Fill out the printReg function.	2009-06-26 22:01:34 -07:00
Jack Whitman	7b5386d390	ARM: Fix signed multiply long and add some unimplemented loads.	2009-06-24 21:22:52 -07:00
Jack Whitman	853a0858f3	ARM: Link register is trashed by non-executed branch and link operations.	2009-06-24 21:22:46 -07:00
Jack Whitman	6dd4272804	ARM: Added unimplemented load/store multiple instructions.	2009-06-23 23:23:25 -07:00
Gabe Black	d744525273	ARM: Simplify some utility functions.	2009-06-21 22:51:13 -07:00
Gabe Black	5c2a362cb7	ARM: Move util functions out of the isa desc.	2009-06-21 22:50:33 -07:00
Gabe Black	d4a03f1900	ARM: Simplify the ISA desc by pulling some classes out of it.	2009-06-21 17:21:25 -07:00
Gabe Black	2a39570b78	ARM: Remove the currently unecessary FPAOp class.	2009-06-21 17:14:51 -07:00
Gabe Black	d1d733f636	ARM: Make inst bitfields accessible outside of the isa desc.	2009-06-21 16:41:21 -07:00
Gabe Black	47e71d674a	ARM: Don't downconvert ExtMachInsts to MachInsts.	2009-06-21 16:41:07 -07:00
Gabe Black	7e4f132369	ARM: Get rid of a few more unused operands.	2009-06-21 09:48:51 -07:00
Gabe Black	4415e2dcd6	ARM: Get rid of unnecessary Re operand.	2009-06-21 09:48:44 -07:00
Gabe Black	7d4ef8a398	ARM: Clear out some inherited hangers on in util.isa and utility.hh.	2009-06-21 09:43:55 -07:00
Gabe Black	5bc1373050	ARM: Get rid of unnecessary fp_enable_checks.	2009-06-21 09:41:04 -07:00
Gabe Black	3964709711	ARM: Adjust simplify rotate_imm slightly.	2009-06-21 09:38:54 -07:00
Gabe Black	c20ce20e4c	ARM: Make the isa parser aware that CPSR is being used.	2009-06-21 09:37:41 -07:00
Gabe Black	71e0d1ded2	ARM: Pull some static code out of the isa desc and create miscregs.hh.	2009-06-21 09:21:07 -07:00
Gabe Black	19a1966079	ARM: Get rid of unused postacc_code.	2009-06-21 09:16:55 -07:00
Gabe Black	b394242240	ARM: Hook in the mmap2 system call. Make ArmLinuxProcess handle 5,6 syscall params.	2009-06-09 23:41:45 -07:00
Gabe Black	c913c64be2	ARM: Add a memory_barrier function to the "comm page". ... This function doesn't actually provide a memory barrier (I don't think they're implemented) and instead just returns.	2009-06-09 23:41:35 -07:00
Gabe Black	3ff1e922c2	ARM: Add a cmpxchg implementation to the "comm page". ... This implementation does what it's supposed to (I think), but it's not atomic and doesn't have memory barriers like the kernel's version.	2009-06-09 23:41:03 -07:00
Gabe Black	37ac2871d5	ARM: Implement TLS. This is not tested.	2009-06-09 23:39:07 -07:00
Gabe Black	5daeefc505	ARM: Make ArmLinuxProcess understand "ARM private" system calls.	2009-06-09 23:38:50 -07:00
Gabe Black	fbf4dc9da2	ARM: Update the kernel version M5 reports to 2.6.16.19	2009-06-09 23:37:41 -07:00
Nathan Binkert	6faf377b53	types: clean up types, especially signed vs unsigned	2009-06-04 23:21:12 -07:00
Gabe Black	7f50ea05ac	X86: Keep track of more descriptor state to accomodate KVM.	2009-05-28 23:27:56 -07:00
Nathan Binkert	47877cf2db	types: add a type for thread IDs and try to use it everywhere	2009-05-26 09:23:13 -07:00
Gabe Black	d93392df28	X86: Really set up the GDT and various hidden/visible segment registers.	2009-05-26 02:23:08 -07:00
Nathan Binkert	8d2e51c7f5	includes: sort includes again	2009-05-17 14:34:52 -07:00
Nathan Binkert	709d859530	includes: use base/types.hh not inttypes.h or stdint.h	2009-05-17 14:34:51 -07:00
Nathan Binkert	eef3a2e142	types: Move stuff for global types into src/base/types.hh ... --HG-- rename : src/sim/host.hh => src/base/types.hh	2009-05-17 14:34:50 -07:00
Korey Sewell	97a04b16eb	mips-merge: merge hello world regress for inorder cpu ... w/latest changes	2009-05-13 02:02:05 -04:00
Nathan Binkert	82c9e6a5fc	gcc: work around a bogus gcc error	2009-05-12 22:33:05 -07:00
Korey Sewell	1f4c954590	inorder-mips: Remove eaComp & memAcc; use 'visible' eaComp ... Inorder expects eaComp to be visible through StaticInst object. This mirrors a similar change to ALPHA... Needs to be done for SPARC and whatever other ISAs want to use InOrderCPU	2009-05-13 01:26:46 -04:00
Korey Sewell	bc69e7947c	arch-mips: add regWidth constant to float regfile	2009-05-13 01:26:38 -04:00
Korey Sewell	5d810c30e6	alpha-isa: add mt.hh so it can compile with inorder	2009-05-12 20:18:34 -04:00
Korey Sewell	db2b721380	inorder-tlb-cunit: merge the TLB as implicit to any memory access ... TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory and the result is checked before it's sent out to memory. * * *	2009-05-12 15:01:16 -04:00
Korey Sewell	6211fe5d2e	inorder-float: Fix storage of FP results ... inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from the actual floating point register file, the model can figure out what it needs to store	2009-05-12 15:01:15 -04:00
Korey Sewell	1c7e988272	inorder-mem: skeleton support for prefetch/writehints	2009-05-12 15:01:15 -04:00
Korey Sewell	5127ea226a	inorder-unified-tlb: use unified TLB instead of old TLB model	2009-05-12 15:01:14 -04:00
Korey Sewell	2012202b06	inorder/alpha-isa: create eaComp object visible to StaticInst through ISA ... Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access * * *	2009-05-12 15:01:14 -04:00
Korey Sewell	b569f8f0ed	inorder-bpred: edits to handle non-delay-slot ISAs ... Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline	2009-05-12 15:01:14 -04:00
Korey Sewell	1c8dfd9254	inorder-alpha-port: initial inorder support of ALPHA ... Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions * * * Remove namespace from header file. Causes compiler issues that are hard to find * * * Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time * * * Expose memory access size and flags through instruction object (temporarily memAccSize and memFlags to get TLB stuff working.)	2009-05-12 15:01:13 -04:00
Korey Sewell	63db33c4b1	isa-parser: made a few changes, but not author-worthy	2009-05-12 15:01:13 -04:00
Gabe Black	7146eb79f1	X86: Precompute the default and alternate address and operand size and the stack size.	2009-04-26 16:49:24 -07:00
Gabe Black	b6bfe8af26	X86: Split out the internal memory space from the regular translate() and precompute mode.	2009-04-26 16:48:44 -07:00
Gabe Black	4ee34dfb4e	X86: Centralize updates to the handy M5 reg.	2009-04-26 16:47:48 -07:00
Gabe Black	2f34a7eaeb	X86: Tell the function that sends int messages who to send to instead of figuring it out itself.	2009-04-26 02:09:27 -07:00
Gabe Black	88ab4bb257	X86: Make the local APICs register themselves with the IO APIC. ... This is a hack so that the IO APIC can figure out information about the local APICs. The local APICs still have no way to find out about each other. Ideally, when the local APICs update state that's relevant to somebody else, they'd send an update to everyone. Without being able to do a broadcast, that would still require knowing who else there is to notify. Other broadcasts are implemented using assumptions that may not always be true.	2009-04-26 02:09:13 -07:00
Gabe Black	c5e2cf841d	X86: Record the initial APIC ID which identifies an APIC in M5. ... The ID as exposed to software can be changed. Tracking those changes in M5 would be cumbersome, especially since there's no guarantee the IDs will remain unique.	2009-04-26 02:06:21 -07:00
Gabe Black	9d0fa27d09	SPARC: Tighten up the clone system call and SPARCs copyRegs.	2009-04-24 23:11:21 -07:00
Gabe Black	ee7055c289	X86: Put the StoreCheck flag with the others, and don't collide with other flags.	2009-04-23 01:43:00 -07:00
Nathan Binkert	43c7698f49	arm: include missing file for arm	2009-04-21 15:40:26 -07:00
Nathan Binkert	50f1570352	arm: Unify the ARM tlb. We forgot about this when we did the rest. ... This code compiles, but there are no tests still	2009-04-21 15:40:25 -07:00
Steve Reinhardt	52b6764f31	syscall: Resolve conflicts between m5threads and Gabe's recent SE changes.	2009-04-21 08:17:36 -07:00
Daniel Sanchez	b0e9654f86	Commit m5threads package. ... This patch adds limited multithreading support in syscall-emulation mode, by using the clone system call. The clone system call works for Alpha, SPARC and x86, and multithreaded applications run correctly in Alpha and SPARC.	2009-04-21 08:17:36 -07:00
Gabe Black	089b384086	X86: Fix the functions that manipulate large bit arrays in the local APIC.	2009-04-19 13:47:15 -07:00
Gabe Black	eee74ba427	X86: Fix up a copyright.	2009-04-19 13:17:35 -07:00
Gabe Black	6910baa015	X86: Fix how the TLB handles the storecheck flag.	2009-04-19 04:57:51 -07:00
Gabe Black	0a6ff60caa	X86: Recognize and handle the lock legacy prefix.	2009-04-19 04:57:28 -07:00
Gabe Black	61edc9ba66	X86: Implement a locking version of XADD.	2009-04-19 04:56:49 -07:00
Gabe Black	209cfc89fd	X86: Implement a locking version of BTC.	2009-04-19 04:56:45 -07:00
Gabe Black	e475cf85f0	X86: Implement a locking version of BTR.	2009-04-19 04:56:43 -07:00
Gabe Black	43f58927d6	X86: Implement a locking version of CMPXCHG.	2009-04-19 04:56:40 -07:00
Gabe Black	b493906eb9	X86: Implement a locking version of BTS.	2009-04-19 04:56:36 -07:00
Gabe Black	985d959ea6	X86: Implement a locking version of DEC.	2009-04-19 04:56:34 -07:00
Gabe Black	4f2d4f466a	X86: Implement a locking version of INC.	2009-04-19 04:56:31 -07:00
Gabe Black	2394f73f90	X86: Implement a locking version of NEG.	2009-04-19 04:56:28 -07:00
Gabe Black	9b9b7a412c	X86: Implement a locking version of NOT.	2009-04-19 04:56:25 -07:00
Gabe Black	b8f81c62a2	X86: Implement a locking version of XCHG.	2009-04-19 04:56:22 -07:00
Gabe Black	750f5a0a67	X86: Implement a locking version of XOR.	2009-04-19 04:56:20 -07:00
Gabe Black	cfb289ebeb	X86: Implement a locking version of SUB.	2009-04-19 04:56:16 -07:00
Gabe Black	789b3191b9	X86: Implement a locking version of AND.	2009-04-19 04:56:14 -07:00
Gabe Black	e742cad6f4	X86: Implement a locking version of SBB.	2009-04-19 04:56:11 -07:00
Gabe Black	193265c6e5	X86: Implement a locking version of ADC.	2009-04-19 04:56:08 -07:00
Gabe Black	2f607b882c	X86: Implement a locking version of OR.	2009-04-19 04:56:06 -07:00
Gabe Black	a7f79c9049	X86: Implement a locking version of ADD.	2009-04-19 04:56:02 -07:00
Gabe Black	d90456a486	X86: Implement the stul microop. ... This microop does a store and unlocks the requested address. The RISC86 microop ISA doesn't seem to have an equivalent to this, so I'm guessing that the store following an ldstl is automatically unlocking. We don't do it this way for performance reasons since the behavior is the same.	2009-04-19 04:55:58 -07:00
Gabe Black	d2554ff030	X86: Implement the ldstl microop. ... This microop does a load, checks that a store would succeed, and locks the requested address.	2009-04-19 04:55:43 -07:00
Gabe Black	3e5f487663	Memory: Rename LOCKED for load locked store conditional to LLSC.	2009-04-19 04:25:01 -07:00
Gabe Black	ca85981478	SE mode: Make keeping track of the number of syscalls less hacky.	2009-04-19 04:15:32 -07:00
Gabe Black	5f164ba720	X86: Actually handle 16 bit mode modrm.	2009-04-19 04:14:31 -07:00
Gabe Black	93cccf7d19	X86: Make the TEST instruction set all the flags it's supposed to.	2009-04-19 04:14:16 -07:00
Gabe Black	f82c123242	X86: Implement broadcast IPIs.	2009-04-19 04:14:01 -07:00
Gabe Black	829e424353	X86: Fix the ordering of the vendor string reported by CPUID.	2009-04-19 04:13:45 -07:00
Gabe Black	18b3863127	X86: Only recognize the first startup IPI after INIT or reset.	2009-04-19 03:56:36 -07:00
Gabe Black	4d32cd10ce	X86: Use recvResponse to implement the idle bit in the Local APIC ICR.	2009-04-19 03:56:24 -07:00
Gabe Black	bdda224d41	X86: Add a function which gets called when an interrupt message has been delivered.	2009-04-19 03:54:11 -07:00
Gabe Black	3eed59768c	X86: Explicitly use the right width in a few places that need a 64 bit value.	2009-04-19 03:47:59 -07:00
Gabe Black	8761057c78	X86: Keep track of the pioAddr for the local APIC.	2009-04-19 03:47:12 -07:00
Gabe Black	038225a6ca	X86: Implement far jmp.	2009-04-19 03:42:41 -07:00
Gabe Black	3b1b21cb15	X86: Some segment selectors can be used when "NULL".	2009-04-19 03:41:10 -07:00
Gabe Black	a0cc081997	X86: Fix a bug in the chks microop where it ignored that it found a fault.	2009-04-19 03:40:08 -07:00
Gabe Black	f2ff5b9249	X86: Make the interrupt entering microcode record the value to use, not actually use it.	2009-04-19 03:36:57 -07:00
Gabe Black	35eea4191b	X86: LEA calculates an address before segmentation.	2009-04-19 03:24:51 -07:00
Gabe Black	bdd55ec8b6	X86: Implement the save machine status word instruction (SMSW).	2009-04-19 03:22:38 -07:00
Gabe Black	d86cd1d2a0	X86: Implement the load machine status word instruction (LMSW).	2009-04-19 03:17:14 -07:00
Gabe Black	eba640c963	X86: Only use %eax to select a function and look like we support sse2.	2009-04-19 03:11:24 -07:00
Gabe Black	27e54982b4	X86: Fix the mov to segment selector in real mode instruction microcode.	2009-04-19 03:08:40 -07:00
Gabe Black	633c96bd85	X86: The startup IPI delivery mode is not reserved.	2009-04-19 03:01:46 -07:00
Gabe Black	08f021aad0	X86: Implement the STARTUP IPI.	2009-04-19 02:56:03 -07:00
Gabe Black	d277feb925	X86: Implement the INIT IPI.	2009-04-19 02:53:00 -07:00
Gabe Black	a340b214cf	X86: Fix the halt microop.	2009-04-19 02:51:09 -07:00
Gabe Black	641513fe08	X86: Start implementing the interrupt command register in the local APIC.	2009-04-19 02:43:22 -07:00
Gabe Black	05b5861419	X86: Condense the startupCPU code.	2009-04-19 02:20:57 -07:00
Gabe Black	f668340f2c	X86: Set the local APIC ID to something meaningful.	2009-04-19 02:16:49 -07:00
Gabe Black	79a3a6aecb	X86: Don't pretend to be an AMD CPU any more. We're not good enough at it.	2009-04-19 02:06:51 -07:00
Korey Sewell	d8a34a9745	mips-tlb-fix: check for alignment faults.\nMIPS was never updated to use TLBS correcty in SE mode. The error was forwarding translations directly to pageTable. The TLB should check for alignment faults at bare minimum here but in the long run we should be using TLBs in SE mode for MIPS.	2009-04-18 10:42:29 -04:00
Korey Sewell	e501e1af54	mips-syscall: mark with correct flag. \nMIPS was using wrong serialization flag on syscall instructions allowing O3 to handle SE mode syscalls incorrectly and speculate on instructions after a syscall	2009-04-18 10:42:29 -04:00
Korey Sewell	5c1742b822	o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode stage was not setting the predicted PC correctly or passing that information back to fetch correctly	2009-04-18 10:42:29 -04:00
Korey Sewell	cc9e834e93	mips-shadowsets: fix calcuations. \n Remove Shadowsets from Int & Arch. Reg Calculations	2009-04-18 10:42:28 -04:00
Steve Reinhardt	8882dc1283	Get rid of the Unallocated thread context state. ... Basically merge it in with Halted. Also had to get rid of a few other functions that called ThreadContext::deallocate(), including: - InOrderCPU's setThreadRescheduleCondition. - ThreadContext::exit(). This function was there to avoid terminating simulation when one thread out of a multi-thread workload exits, but we need to find a better (non-cpu-centric) way.	2009-04-15 13:13:47 -07:00
Gabe Black	5c79191603	X86: Fix minor bug in the page table walker from TLB shuffling.	2009-04-13 04:14:15 -07:00
Nathan Binkert	18a30524d6	alpha: get rid of all turbolaser remnants	2009-04-08 22:22:49 -07:00
Nathan Binkert	e0de2c3443	tlb: More fixing of unified TLB	2009-04-08 22:21:27 -07:00
Gabe Black	7b5a96f06b	tlb: Don't separate the TLB classes into an instruction TLB and a data TLB	2009-04-08 22:21:27 -07:00
Gabe Black	d080581db1	Merge ARM into the head. ARM will compile but may not actually work.	2009-04-06 10:19:36 -07:00
Stephen Hines	7a7c4c5fca	arm: add ARM support to M5	2009-04-05 18:53:15 -07:00
Nathan Binkert	ac64586a99	build: fix compiler warnings in g++ 3.4	2009-03-07 21:34:50 -08:00
Nathan Binkert	cc95b57390	stats: Fix all stats usages to deal with template fixes	2009-03-05 19:09:53 -08:00
Steve Reinhardt	e3d6e8882e	Get rid of 'using namespace' declarations in headers.	2009-03-05 17:15:31 -08:00
Steve Reinhardt	307905095c	Fix Num_Syscall_Descs check bug in non-x86 ISAs. ... (See cset d35d2b28df38 for x86 fix.)	2009-02-28 20:14:22 -05:00
Nathan Binkert	4523741c1c	quell gcc 4.3 warning	2009-02-27 17:29:58 -08:00
Gabe Black	b69a9ad45a	X86: Install the exit system call.	2009-02-27 09:26:41 -08:00
Gabe Black	9265b3d598	X86: Install the 32 bit write system call.	2009-02-27 09:26:32 -08:00
Gabe Black	b36f28472d	X86: Implement shrd.	2009-02-27 09:26:26 -08:00
Gabe Black	2fe87e62ba	X86: Add a structure to allow mapping between the host and guest fstat formats.	2009-02-27 09:26:17 -08:00
Gabe Black	27b751ec46	X86: Don't treat the REX prefixes as prefixes in 32 bit modes. These are inc/dec instructions.	2009-02-27 09:26:09 -08:00
Gabe Black	aa51c01d69	X86: Set address size to 64 bits when generating addresses internally.	2009-02-27 09:26:01 -08:00
Gabe Black	db3c51d3a0	X86: Add a vsyscall page for 32 bit processes to use.	2009-02-27 09:25:51 -08:00
Gabe Black	c3d7d7ed0e	X86: Implement sysenter as a system call interface.	2009-02-27 09:25:43 -08:00
Gabe Black	5c1cc99d48	X86: Add a 32 bit mmap2 system call.	2009-02-27 09:25:33 -08:00
Gabe Black	04dbed79f8	X86: Install a 32 bit fstat64 system call.	2009-02-27 09:25:26 -08:00
Gabe Black	8a1eb7e8be	X86: Take address size into account when computing an effective address.	2009-02-27 09:25:16 -08:00
Gabe Black	1d18eb9043	X86: Make instructions that use intseg preserve all 8 bytes of their addresses.	2009-02-27 09:25:02 -08:00
Gabe Black	79bc1b3740	X86: Fix a decoder bug and add in some missing instructions.	2009-02-27 09:24:10 -08:00
Gabe Black	3dfa564e70	X86: Respect segment override prefixes even when there's no ModRM byte.	2009-02-27 09:23:58 -08:00
Gabe Black	9dfa3f7f73	X86: Fix segment limit checks.	2009-02-27 09:23:50 -08:00
Gabe Black	9491debaa6	X86: Implement the 32 bit set_thread_area system call.	2009-02-27 09:23:42 -08:00
Gabe Black	1786f20058	X86: Set an initial value for the LDT selector.	2009-02-27 09:23:27 -08:00
Gabe Black	e23d688d8f	X86: Set up a space for a GDT in SE so we can set up TLS or LDT segments.	2009-02-27 09:23:17 -08:00
Gabe Black	281ef8111a	X86: Compute shift instruction flags correctly.	2009-02-27 09:23:00 -08:00
Gabe Black	14fc06640e	X86: Install some 32 bit system calls.	2009-02-27 09:22:50 -08:00
Gabe Black	6ca53f8675	X86: Handle 32 bit system call arguments.	2009-02-27 09:22:30 -08:00
Gabe Black	9a000c5173	Processes: Make getting and setting system call arguments part of a process object.	2009-02-27 09:22:14 -08:00
Gabe Black	60aab03e85	X86: Implement the int system call interface in the decoder.	2009-02-27 09:21:58 -08:00
Gabe Black	05de9f4e2c	X86: Distinguish the width of values on the stack between 32 and 64 bit processes.	2009-02-27 09:21:36 -08:00
Gabe Black	932f6440a1	X86: Add a class to support 32 bit x86 linux process.	2009-02-27 09:21:14 -08:00
Ali Saidi	d447ccb2c6	CPA: Add code to automatically record function symbols as CPU executes.	2009-02-26 19:29:17 -05:00
Ali Saidi	6fd4bc34a1	CPA: Add new object for gathering critical path annotations.	2009-02-26 19:29:17 -05:00
Gabe Black	7400769768	X86: Implement IST stack switching.	2009-02-25 10:22:43 -08:00
Gabe Black	437b02884d	ISA: Get rid of the get*RegName functions.	2009-02-25 10:22:31 -08:00
Gabe Black	3b01535ec1	SPARC: Get rid of the state keeping track of register frames.	2009-02-25 10:22:25 -08:00
Gabe Black	4633677145	ISA: Set up common trace flags for tracing registers.	2009-02-25 10:22:17 -08:00
Gabe Black	44d5351071	ISA: Get rid of FlattenIntIndex function.	2009-02-25 10:22:09 -08:00
Gabe Black	c1c61d52a0	SPARC: Get rid of flattenIndex in the int register file.	2009-02-25 10:21:59 -08:00
Gabe Black	ce2e50a64c	ISA: Use the "Stack" traceflag for DPRINTFs about the initial stack frame.	2009-02-25 10:21:52 -08:00
Gabe Black	9d5b6e377f	SPARC: Get rid of the setGlobals function.	2009-02-25 10:21:46 -08:00
Gabe Black	f41ce6b5e9	SPARC: Get rid of the setCWP function.	2009-02-25 10:21:40 -08:00
Gabe Black	88ee7d4c32	SPARC: Add a traceflag for register windows.	2009-02-25 10:21:33 -08:00
Gabe Black	7aa875f4f3	X86: Implement the lldt instruction.	2009-02-25 10:21:27 -08:00
Gabe Black	bda7077c64	X86: Add segmentation checks for ldt related descriptors and selectors.	2009-02-25 10:21:21 -08:00
Gabe Black	e08d60389d	X86: Make the TSS type check actually return a fault if it fails.	2009-02-25 10:21:14 -08:00
Gabe Black	68300cfb8c	X86: Make rdcr use merge and the mov to control register instructions use the right operand size.	2009-02-25 10:21:08 -08:00
Gabe Black	9842f1ca9d	X86: Implement CLTS.	2009-02-25 10:21:02 -08:00
Gabe Black	b035c917a5	X86: Make the segment register reading microops use merge.	2009-02-25 10:20:47 -08:00
Gabe Black	28efb3c6e3	X86: Implement the mov to debug register intructions.	2009-02-25 10:20:42 -08:00
Gabe Black	c39ed53d05	X86: Rename oszForPseudoDesc maxOsz to reflect its more general use.	2009-02-25 10:20:30 -08:00
Gabe Black	3ca2451d81	X86: Add code to interpret debug register values.	2009-02-25 10:20:25 -08:00
Gabe Black	1e70401c08	X86: Fix a few bugs with the segment register instructions in real mode. ... Fix a few instances where the register form of zext was used where zexti was intended. Also get rid of the 64 bit only rip relative addressed version since 64 bit and real mode are mutually exclusive.	2009-02-25 10:20:19 -08:00
Gabe Black	8813168b5a	X86: Do a merge for the zero extension microop.	2009-02-25 10:20:10 -08:00
Gabe Black	28a35a6adb	X86: Add microops for reading/writing debug registers.	2009-02-25 10:20:01 -08:00
Gabe Black	11fbed02ea	X86: Add classes that break out the bits of the DR6 and DR7 registers.	2009-02-25 10:19:54 -08:00
Gabe Black	cb4141f6e6	X86: Check src1 for illegal values since that's the index we actually use.	2009-02-25 10:19:47 -08:00
Gabe Black	d48214a656	X86: Implement the fence instructions. These are not microcoded.	2009-02-25 10:19:41 -08:00
Gabe Black	06ff83e1b9	X86: Implement a basic prefetch instruction.	2009-02-25 10:19:22 -08:00
Gabe Black	5f0428ef9f	X86: Use the right portion of a register for stores.	2009-02-25 10:19:14 -08:00
Gabe Black	c849ef58c0	X86: Actually check page protections.	2009-02-25 10:18:58 -08:00
Gabe Black	f35a37ca9e	X86: Update CS later so stack accesses have the right permission checks.	2009-02-25 10:18:51 -08:00
Gabe Black	ba69184630	X86: Use atCPL0 for accesses that are part of CPU machinery.	2009-02-25 10:18:29 -08:00
Gabe Black	dc53ca89f6	X86: Add a flag to force memory accesses to happen at CPL 0.	2009-02-25 10:18:22 -08:00
Gabe Black	897c374892	X86: Move where CS is set so CPL checks work out.	2009-02-25 10:18:16 -08:00
Gabe Black	710b43dfbd	X86: Implement inUserMode for x86.	2009-02-25 10:18:06 -08:00
Gabe Black	1cedc748d4	X86: Add a trace flag for tracing faults.	2009-02-25 10:17:59 -08:00
Gabe Black	eec3f49a57	X86: Implement the sysret instruction in long mode.	2009-02-25 10:17:54 -08:00
Gabe Black	6325245e3e	X86: Implement the longmode versions of the syscall instruction.	2009-02-25 10:17:49 -08:00
Gabe Black	dadc30b0a4	X86: Make the microcode assembler recognize r8-r15.	2009-02-25 10:17:43 -08:00
Gabe Black	fcad6e3b13	X86: Add a wrattr microop.	2009-02-25 10:17:38 -08:00
Gabe Black	e4ede69b2f	X86: Add a trace flag for the page table walker.	2009-02-25 10:17:27 -08:00
Gabe Black	99aa121fca	X86: Make exceptions handle stack switching.	2009-02-25 10:17:19 -08:00
Gabe Black	aa7bc1be74	X86: Implement the LTR instruction.	2009-02-25 10:17:14 -08:00
Gabe Black	08f3a126d5	X86: Fix segment limit checking.	2009-02-25 10:17:08 -08:00
Gabe Black	2f31643db5	X86: Add a check to chks to verify a task state segment descriptor.	2009-02-25 10:17:02 -08:00
Gabe Black	7b1cb74ac3	X86: Add a check to chks which raises #GP(selector) if selector is NULL or not in the GDT.	2009-02-25 10:16:54 -08:00
Gabe Black	82288e7c3e	X86: Add makeAtomicResponse to the read/write functions of x86 devices.	2009-02-25 10:16:43 -08:00
Gabe Black	7462cb0842	X86: Fix the timing mode of the page table walker.	2009-02-25 10:16:34 -08:00
Gabe Black	40fdba2454	X86: Make the X86 TLB take advantage of delayed translations, and get rid of the fake TLB miss faults.	2009-02-25 10:16:21 -08:00
Gabe Black	6ed47e9464	CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it.	2009-02-25 10:16:15 -08:00
Gabe Black	15940d06b5	SPARC: Adjust a few instructions to not write registers in initiateAcc.	2009-02-25 10:16:04 -08:00
Gabe Black	1b336a8fe7	X86: Make the stupd microop not update registers in initiateAcc.	2009-02-25 10:15:56 -08:00
Gabe Black	5605079b1f	ISA: Replace the translate functions in the TLBs with translateAtomic.	2009-02-25 10:15:44 -08:00
Gabe Black	a1aba01a02	CPU: Get rid of translate... functions from various interface classes.	2009-02-25 10:15:34 -08:00
Nathan Binkert	3fa9812e1d	debug: Move debug_break into src/base	2009-02-23 11:48:40 -08:00
Gabe Black	e8c1c3e72e	X86: Pass whether an access was a read/write/fetch so faults can behave accordingly.	2009-02-23 00:20:34 -08:00
Korey Sewell	6c5afe6346	Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up comments and O3 extensions InOrder Thread Context	2009-02-20 11:02:48 -05:00
Lisa Hsu	5d029ff11e	sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though.	2009-02-16 17:47:39 -05:00
Korey Sewell	36d9065f5f	syscall: Expose ioctl for MIPS	2009-02-10 15:49:29 -08:00
Nathan Binkert	20c5ec6e1c	copyright: This file need not have had the more restrictive copyright.	2009-02-09 20:10:15 -08:00
Nathan Binkert	dd6ea8797f	scons: Require SCons version 0.98.1 ... This allows me to clean things up so we are up to date with respect to deprecated features. There are many features scheduled for permanent failure in scons 2.0 and 0.98.1 provides the most compatability for that. It also paves the way for some nice new features that I will add soon	2009-02-09 20:10:14 -08:00
Nathan Binkert	e1798d063e	Quell g++ 4.3 warning about operator ambiguity	2009-02-06 20:55:50 -08:00
Gabe Black	5a4eed5d34	X86: All x86 fault classes now attempt to do something useful.	2009-02-01 17:09:08 -08:00
Gabe Black	923a14dde7	X86: Make the fault classes handle error codes better.	2009-02-01 17:08:32 -08:00
Gabe Black	2f8cec849d	X86: Make the long mode interrupt/exception microcode handle an error code.	2009-02-01 17:07:43 -08:00
Gabe Black	9b4d1e0f9a	X86: Distinguish between hardware and software interrupts/exceptions	2009-02-01 17:07:18 -08:00
Gabe Black	041402a949	X86: Fix the upper bound on some ranges that were setting up the micro code assembler.	2009-02-01 17:06:25 -08:00
Gabe Black	6b53b8387e	X86: Make the chks microop check for the right int descriptor type.	2009-02-01 17:05:37 -08:00
Gabe Black	c0cd58812e	X86: Touch up the interrupt entering microcode.	2009-02-01 17:04:21 -08:00
Gabe Black	03a00735c2	X86: Keep track of the vector for all exceptions/faults.	2009-02-01 17:03:11 -08:00
Gabe Black	6b60a29706	X86: Fix the time keeping of the Local APIC timer.	2009-02-01 00:30:11 -08:00
Gabe Black	ca6e0d75c8	X86: Fix the microcode for the LODS instruction.	2009-02-01 00:28:28 -08:00
Gabe Black	d432bd13b2	X86: Fix some incorrect register widths.	2009-02-01 00:18:13 -08:00
Gabe Black	f3b8371dfc	X86: Add extended Intel MP entries correctly.	2009-02-01 00:15:38 -08:00
Gabe Black	06cdbe5ea7	X86: Compute PCI config addresses correctly.	2009-02-01 00:11:49 -08:00
Gabe Black	483c3e96b7	X86: Calculate flags based on the actual result.	2009-02-01 00:08:16 -08:00
Gabe Black	953e4bba59	X86: Set/correct some default values for x86 parameters.	2009-02-01 16:59:34 -08:00
Ali Saidi	e7293dd24e	Errors: Use the correct panic/warn/fatal/info message in some places.	2009-01-30 20:04:17 -05:00
Gabe Black	52defeb4e7	X86: Implement the xadd instruction.	2009-01-25 20:33:27 -08:00
Gabe Black	3c5988b86c	X86: Implement the bswap instruction.	2009-01-25 20:32:43 -08:00
Gabe Black	0449fb2b7a	X86: Fix a bug in the iret microcode.	2009-01-25 20:31:17 -08:00
Gabe Black	389fbfdab1	X86: Make the interrupt object wake up the CPU when something becomes pending.	2009-01-25 20:30:51 -08:00
Gabe Black	d9794784ba	CPU: Add a setCPU function to the interrupt objects.	2009-01-25 20:29:03 -08:00
Nathan Binkert	64ed39f61b	pseudo inst: Add new wake cpu instruction for sending a message to wake a cpu. ... It's instantaneous and so it's somewhat bogus, but it's a first step.	2009-01-24 07:27:22 -08:00
Nathan Binkert	c9d3113015	tracing: Add help strings for some of the trace flags	2009-01-19 09:59:14 -08:00
Nathan Binkert	8153790d00	SCons: centralize the Dir() workaround for newer versions of scons. ... Scons bug id: 2006 M5 Bug id: 308	2009-01-13 14:17:50 -08:00
Gabe Black	b23633ad1b	X86: Hook in the M5 pseudo insts.	2009-01-06 23:55:46 -08:00
Gabe Black	115b1a7ed3	X86: Autogenerate macroop generateDisassemble function.	2009-01-06 22:55:27 -08:00
Gabe Black	8cab1805f9	X86: Move the function that prints memory args into the inst base class.	2009-01-06 22:46:28 -08:00
Gabe Black	9e24d8c599	X86: Move the macroop class out of the isa description into C++.	2009-01-06 22:44:59 -08:00
Gabe Black	7b7a72158a	X86: Change indentation on microop disassembly.	2009-01-06 22:40:41 -08:00
Steve Reinhardt	1704ba2273	Make Alpha pseudo-insts available from SE mode.	2008-12-17 09:51:18 -08:00
Gabe Black	02cd18f536	SPARC: Truncate syscall args and return values appropriately.	2008-12-16 23:06:37 -08:00
Lisa Hsu	993b7be4bb	imported patch aux-fix.patch	2008-12-07 15:07:42 -05:00
Gabe Black	e4790bcbe2	X86: Add add_entry back in.	2008-12-06 14:48:59 -08:00
Nathan Binkert	e141cb7441	flags: Change naming of functions to be clearer	2008-12-06 14:18:18 -08:00
Lisa Hsu	f1430941cf	This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs.	2008-12-05 12:09:29 -05:00
Lisa Hsu	e2c7618e50	This patch pulls out the auxiliary vector struct from individual ISA ... LiveProcesses to the base LiveProcess definition so anyone can use them.	2008-12-04 18:03:35 -05:00
Steve Reinhardt	4514f565e3	syscalls: fix latent brk/obreak bug. ... Bogus calls to ChunkGenerator with negative size were triggering a new assertion that was added there. Also did a little renaming and cleanup in the process.	2008-11-15 09:30:10 -08:00
Nathan Binkert	5711282f87	Fix a bunch of bugs I introduced when I changed the flags stuff for packets. ... I did some of the flags and assertions wrong. Thanks to Brad Beckmann for pointing this out. I should have run the opt regressions instead of the fast. I also screwed up some of the logical functions in the Flags class.	2008-11-14 04:55:30 -08:00
Nathan Binkert	eb5d9ba72b	pseudo inst: Add rpns (read processor nanoseconds) instruction. ... This instruction basically returns the number of nanoseconds that the CPU has been running.	2008-11-10 11:51:18 -08:00
Nathan Binkert	9c49bc7b00	mem: update stuff for changes to Packet and Request	2008-11-10 11:51:17 -08:00
Gabe Black	8c15518f30	X86: Fix completeAcc get call.	2008-11-09 21:55:43 -08:00
Nathan Binkert	44839d6b71	Fix a few more places where the context stuff wasn't changed	2008-11-05 07:20:03 -08:00
Lisa Hsu	dd99ff23c6	get rid of all instances of readTid() and getThreadNum(). Unify and eliminate ... redundancies with threadId() as their replacement.	2008-11-04 11:35:42 -05:00
Lisa Hsu	d857faf073	Add in Context IDs to the simulator. From now on, cpuId is almost never used, ... the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate.	2008-11-02 21:57:07 -05:00
Lisa Hsu	67fda02dda	Make it so that all thread contexts are registered with the System, even in ... SE. Process still keeps track of the tc's it owns, but registration occurs with the System, this eases the way for system-wide context Ids based on registration.	2008-11-02 21:57:06 -05:00
Lisa Hsu	c55a467a06	make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered ... across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch.	2008-11-02 21:56:57 -05:00
Nathan Binkert	9836d81c2b	style: Use the correct m5 style for things relating to interrupts.	2008-10-21 07:12:53 -07:00
Ali Saidi	b760b99f4d	O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes ... the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal call sys and thus the translation fails because the user is attempting to access a super page address. Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs. Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were removed since a great deal of manual patching would be required to only remove the hwrei change.	2008-10-20 16:22:59 -04:00
Nathan Binkert	81f5da1e89	get rid of local variable that's only used in an assert so fast compiles	2008-10-16 22:22:17 -07:00
Gabe Black	3c4567f2a6	X86: Set the delayed commit flag in x86 microops appropriately.	2008-10-12 23:29:10 -07:00
Gabe Black	33ebd04474	X86: Make the local APIC timer event generate an interrupt.	2008-10-12 23:28:49 -07:00
Gabe Black	bdc28d793d	X86: Implement the EOI register in the local APIC.	2008-10-12 23:28:11 -07:00
Gabe Black	fd37688294	X86: Add some DPRINTFs to the local APIC.	2008-10-12 23:27:45 -07:00
Gabe Black	e3004c579f	X86: Fix the segment setting code in IRET, and make it restore the flags.	2008-10-12 23:05:22 -07:00
Gabe Black	349a155b6e	X86: Panic when an unimplemented fault is invoked, rather than spinning forever	2008-10-12 23:00:28 -07:00
Gabe Black	564eda827b	X86: Implement the swapgs instruction.	2008-10-12 23:00:07 -07:00
Gabe Black	a2e0d539d8	X86: Add wrval/rdval microops for reading significant miscregs.	2008-10-12 22:55:55 -07:00
Gabe Black	9e8e2f9ec6	X86: Make the x86 interrupt fault kick off the interrupt microcode.	2008-10-12 22:42:10 -07:00
Gabe Black	4c19c56a77	X86: Implement entering an interrupt in microcode.	2008-10-12 22:42:03 -07:00
Gabe Black	f813a4be49	X86: Make sure register microops set fault rather than returning one.	2008-10-12 22:24:06 -07:00
Gabe Black	961b40cdb5	X86: Implement an wrdh microop which loads bases/offsets from 16 byte descriptors.	2008-10-12 22:16:53 -07:00
Gabe Black	6074b1abf2	X86: Implement local labels for the ROM that actually refer into the ROM.	2008-10-12 20:44:11 -07:00
Gabe Black	6b46e5204d	X86: Implement the chks check of interrupt gate target code segments.	2008-10-12 20:38:22 -07:00
Gabe Black	30feb90c1c	X86: Add a check type for interrupt gates.	2008-10-12 20:33:37 -07:00
Gabe Black	15f5bb3055	X86: Fix chks checking the submode for stack segments.	2008-10-12 20:29:52 -07:00
Gabe Black	9e1fe2050a	X86: Let segment manipulation microops be conditional.	2008-10-12 20:25:06 -07:00
Gabe Black	e9158d763a	X86: Let the microassembler know about the microcode only H segment.	2008-10-12 20:17:38 -07:00
Gabe Black	223fc41c07	X86: Fix the rdbase microop	2008-10-12 20:07:46 -07:00
Gabe Black	f245358343	Get rid of old RegContext code.	2008-10-12 17:57:46 -07:00
Gabe Black	cefb768131	X86: Create a handy way to access labels from the ROM in microcode.	2008-10-12 17:52:51 -07:00
Gabe Black	e5f8092467	X86: Make X86's microcode ROM actually do something.	2008-10-12 17:48:44 -07:00
Gabe Black	2736086d7c	CPU: Create a microcode ROM object in the CPU which is defined by the ISA.	2008-10-12 15:59:21 -07:00
Gabe Black	6fd4eff68f	X86: Create an eret microop which returns from ROM to combinational decoding.	2008-10-12 15:53:04 -07:00
Gabe Black	4aa18aa800	X86: Make Br never report itself as the last microop.	2008-10-12 15:43:35 -07:00
Gabe Black	77c0e1d110	X86: Create a SeqOp class of microops and make Br one of them.	2008-10-12 15:33:17 -07:00
Gabe Black	a76c4b8ca1	X86: Implement CPUID with a magical function instead of microcode.	2008-10-12 15:31:28 -07:00
Gabe Black	d0a43ce2b2	X86: Fix the ordering of special physical address ranges.	2008-10-12 14:01:06 -07:00
Gabe Black	ec9d3aad71	X86: Make the local APIC process interrupts and send them to the CPU.	2008-10-12 13:45:21 -07:00
Gabe Black	876f4845f2	X86: Make the local APIC handle interrupt messages from the IO APIC.	2008-10-12 13:44:24 -07:00
Gabe Black	3420ad7644	X86: Make the bases for x86 fault class public.	2008-10-12 13:29:26 -07:00
Gabe Black	557bde43c3	X86: Make APICs communicate through the memory system.	2008-10-12 13:28:54 -07:00
Gabe Black	e0f137a87c	X86: Add a LocalApic trace flag.	2008-10-12 12:07:25 -07:00