ARM: Add a register, immediate, immediate to register base for [su]bfx.
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504ac6518b
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b1158e4938
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@ -196,6 +196,18 @@ RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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return ss.str();
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}
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std::string
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RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss);
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printReg(ss, dest);
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ss << ", ";
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printReg(ss, op1);
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ccprintf(ss, ", #%d, #%d", imm1, imm2);
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return ss.str();
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}
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std::string
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RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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@ -176,6 +176,24 @@ class RegRegRegOp : public PredOp
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class RegRegImmImmOp : public PredOp
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{
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protected:
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IntRegIndex dest;
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IntRegIndex op1;
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uint32_t imm1;
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uint32_t imm2;
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RegRegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1,
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uint32_t _imm1, uint32_t _imm2) :
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PredOp(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class RegImmRegShiftOp : public PredOp
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{
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protected:
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@ -196,6 +196,32 @@ def template RegRegRegOpConstructor {{
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}
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}};
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def template RegRegImmImmOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1,
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uint32_t _imm1, uint32_t _imm2);
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%(BasicExecDeclare)s
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};
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}};
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def template RegRegImmImmOpConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest,
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IntRegIndex _op1,
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uint32_t _imm1,
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uint32_t _imm2)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _imm1, _imm2)
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{
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%(constructor)s;
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}
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}};
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def template RegImmRegOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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