Lisa Hsu d6da172517 util: do checkpoint aggregation more cleanly, fix last changeset. ... 1) Move alpha-specific code out of page_table.cc:serialize(). 2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up. 3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN. 4) Fix the memory unserialize that I forgot somehow in the last changeset. 5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py. Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.		2010-01-19 22:03:44 -08:00
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alpha	util: do checkpoint aggregation more cleanly, fix last changeset.	2010-01-19 22:03:44 -08:00
arm	ARM: Begin implementing CP15	2009-11-17 18:02:09 -06:00
mips	MIPS: Beef up process initialization.	2009-12-31 15:30:51 -05:00
power	Syscalls: Make system calls access arguments like a stack, not an array.	2009-10-30 00:44:55 -07:00
sparc	Syscalls: Make system calls access arguments like a stack, not an array.	2009-10-30 00:44:55 -07:00
x86	X86: Add a common named flag for signed media operations.	2009-12-19 01:48:31 -08:00
isa_parser.py	compile: wrap 64bit numbers with ULL() so 32bit compiles work	2009-11-08 13:31:59 -08:00
micro_asm.py	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	Registers: Add a registers.hh file as an ISA switched header.	2009-07-08 23:02:21 -07:00