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ARM: Add support for the clidr register.

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This register will always report 0 caches as implemented. It's not clear how
to find out how many there really are when dealing with an arbitrary
hierarchy.
This commit is contained in:
Gabe Black 2010-06-02 12:58:09 -05:00
parent 896c7617c4
commit e658b6fed4
2 changed files with 8 additions and 3 deletions
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5
src/arch/arm/isa.hh
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@ -164,6 +164,11 @@ namespace ArmISA
panic("Unimplemented CP15 register %s read.\n",
miscRegName[misc_reg]);
}
switch (misc_reg) {
case MISCREG_CLIDR:
warn("The clidr register always reports 0 caches.\n");
break;
}
return readMiscRegNoEffect(misc_reg);
}

6
src/arch/arm/miscregs.hh
View file

@ -92,6 +92,7 @@ namespace ArmISA
MISCREG_CP15DSB,
MISCREG_CP15DMB,
MISCREG_CPACR,
MISCREG_CLIDR,
MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR,
@ -113,7 +114,6 @@ namespace ArmISA
MISCREG_ID_ISAR4,
MISCREG_ID_ISAR5,
MISCREG_CCSIDR,
MISCREG_CLIDR,
MISCREG_AIDR,
MISCREG_CSSELR,
MISCREG_ACTLR,
@ -160,12 +160,12 @@ namespace ArmISA
"fpsr", "fpsid", "fpscr", "fpexc",
"sctlr", "dccisw", "dccimvac",
"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
"cp15isb", "cp15dsb", "cp15dmb", "cpacr",
"cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr",
"ctr", "tcmtr", "mpuir", "mpidr", "midr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
"ccsidr", "clidr", "aidr", "csselr", "actlr",
"ccsidr", "aidr", "csselr", "actlr",
"dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
"drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
"rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",