ARM: Add base classes suitable for the REV* instructions.

src/arch/arm/insts/misc.cc

@@ -142,3 +142,14 @@ MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     printReg(ss, op1);
     return ss.str();
 }
+
+std::string
+RevOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMnemonic(ss);
+    printReg(ss, dest);
+    ss << ", ";
+    printReg(ss, op1);
+    return ss.str();
+}

src/arch/arm/insts/misc.hh

@@ -94,4 +94,18 @@ class MsrRegOp : public MsrBase
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
+class RevOp : public PredOp
+{
+  protected:
+    IntRegIndex dest;
+    IntRegIndex op1;
+
+    RevOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+          IntRegIndex _dest, IntRegIndex _op1) :
+        PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 #endif

src/arch/arm/isa/templates/misc.isa

@@ -98,3 +98,24 @@ def template MsrImmConstructor {{
         %(constructor)s;
     }
 }};
+
+def template RevOpDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+  protected:
+    public:
+        // Constructor
+        %(class_name)s(ExtMachInst machInst,
+                       IntRegIndex _dest, IntRegIndex _op1);
+        %(BasicExecDeclare)s
+};
+}};
+
+def template RevOpConstructor {{
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+                                          IntRegIndex _dest, IntRegIndex _op1)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
+    {
+        %(constructor)s;
+    }
+}};