ARM: Start over with translation from Alpha code as opposed to something that has cruft from 4 different ISAs.
This commit is contained in:
Ali Saidi
parent
237c0617a0
commit
3aea20d143
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@ -57,7 +57,6 @@ if env['TARGET_ISA'] == 'arm':
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Source('insts/vfp.cc')
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Source('miscregs.cc')
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Source('nativetrace.cc')
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Source('pagetable.cc')
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Source('tlb.cc')
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Source('vtophys.cc')
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Source('utility.cc')
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@ -1,78 +0,0 @@
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/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Steve Reinhardt
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* Jaidev Patwardhan
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* Stephen Hines
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*/
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#include "arch/arm/pagetable.hh"
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#include "sim/serialize.hh"
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namespace ArmISA
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{
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void
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PTE::serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(Mask);
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SERIALIZE_SCALAR(VPN);
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SERIALIZE_SCALAR(asid);
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SERIALIZE_SCALAR(G);
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SERIALIZE_SCALAR(PFN0);
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SERIALIZE_SCALAR(D0);
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SERIALIZE_SCALAR(V0);
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SERIALIZE_SCALAR(C0);
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SERIALIZE_SCALAR(PFN1);
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SERIALIZE_SCALAR(D1);
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SERIALIZE_SCALAR(V1);
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SERIALIZE_SCALAR(C1);
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SERIALIZE_SCALAR(AddrShiftAmount);
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SERIALIZE_SCALAR(OffsetMask);
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}
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void
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PTE::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(Mask);
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UNSERIALIZE_SCALAR(VPN);
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UNSERIALIZE_SCALAR(asid);
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UNSERIALIZE_SCALAR(G);
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UNSERIALIZE_SCALAR(PFN0);
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UNSERIALIZE_SCALAR(D0);
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UNSERIALIZE_SCALAR(V0);
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UNSERIALIZE_SCALAR(C0);
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UNSERIALIZE_SCALAR(PFN1);
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UNSERIALIZE_SCALAR(D1);
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UNSERIALIZE_SCALAR(V1);
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UNSERIALIZE_SCALAR(C1);
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UNSERIALIZE_SCALAR(AddrShiftAmount);
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UNSERIALIZE_SCALAR(OffsetMask);
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}
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}
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@ -1,7 +1,17 @@
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -29,8 +39,7 @@
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*
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* Authors: Nathan Binkert
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* Steve Reinhardt
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* Jaidev Patwardhan
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* Stephen Hines
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* Ali Saidi
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*/
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#ifndef __ARCH_ARM_PAGETABLE_H__
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@ -43,59 +52,65 @@
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namespace ArmISA {
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struct VAddr
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struct VAddr
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{
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VAddr(Addr a) { panic("not implemented yet."); }
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};
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// ITB/DTB page table entry
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struct PTE
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{
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void serialize(std::ostream &os)
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{
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static const int ImplBits = 43;
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static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
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static const Addr UnImplMask = ~ImplMask;
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panic("Need to implement PTE serialization\n");
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}
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VAddr(Addr a) : addr(a) {}
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Addr addr;
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operator Addr() const { return addr; }
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const VAddr &operator=(Addr a) { addr = a; return *this; }
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Addr vpn() const { return (addr & ImplMask) >> PageShift; }
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Addr page() const { return addr & Page_Mask; }
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Addr offset() const { return addr & PageOffset; }
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Addr level3() const
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{ return ArmISA::PteAddr(addr >> PageShift); }
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Addr level2() const
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{ return ArmISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
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Addr level1() const
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{ return ArmISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
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};
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// ITB/DTB page table entry
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struct PTE
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void unserialize(Checkpoint *cp, const std::string §ion)
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{
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Addr Mask; // What parts of the VAddr (from bits 28..11) should be used in translation (includes Mask and MaskX from PageMask)
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Addr VPN; // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11 from EntryHi)
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uint8_t asid; // Address Space ID (8 bits) // Lower 8 bits of EntryHi
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panic("Need to implement PTE serialization\n");
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}
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bool G; // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit
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};
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/* Contents of Entry Lo0 */
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Addr PFN0; // Physical Frame Number - Even
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bool D0; // Even entry Dirty Bit
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bool V0; // Even entry Valid Bit
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uint8_t C0; // Cache Coherency Bits - Even
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// ITB/DTB table entry
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struct TlbEntry
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{
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Addr tag; // virtual page number tag
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Addr ppn; // physical page number
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uint8_t asn; // address space number
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bool valid; // valid page table entry
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/* Contents of Entry Lo1 */
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Addr PFN1; // Physical Frame Number - Odd
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bool D1; // Odd entry Dirty Bit
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bool V1; // Odd entry Valid Bit
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uint8_t C1; // Cache Coherency Bits (3 bits)
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/* The next few variables are put in as optimizations to reduce TLB lookup overheads */
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/* For a given Mask, what is the address shift amount, and what is the OffsetMask */
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int AddrShiftAmount;
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int OffsetMask;
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//Construct an entry that maps to physical address addr.
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TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr)
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{
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tag = _vaddr >> PageShift;
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ppn = _paddr >> PageShift;
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asn = _asn;
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valid = true;
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}
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TlbEntry()
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{}
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void
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updateVaddr(Addr new_vaddr)
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{
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tag = new_vaddr >> PageShift;
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}
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Addr
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pageStart()
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{
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return ppn << PageShift;
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}
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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bool Valid() { return (V0 | V1);};
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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};
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#endif // __ARCH_ARM_PAGETABLE_H__
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@ -12,8 +12,6 @@
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -39,10 +37,9 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Authors: Ali Saidi
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* Nathan Binkert
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* Steve Reinhardt
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* Jaidev Patwardhan
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* Stephen Hines
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*/
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#include <string>
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@ -64,19 +61,12 @@
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using namespace std;
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using namespace ArmISA;
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///////////////////////////////////////////////////////////////////////
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//
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// ARM TLB
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//
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#define MODE2MASK(X) (1 << (X))
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TLB::TLB(const Params *p)
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: BaseTLB(p), size(p->size), nlu(0)
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{
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table = new ArmISA::PTE[size];
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memset(table, 0, sizeof(ArmISA::PTE[size]));
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smallPages=0;
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}
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TLB::~TLB()
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@ -85,104 +75,10 @@ TLB::~TLB()
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delete [] table;
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}
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// look up an entry in the TLB
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ArmISA::PTE *
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TLB::lookup(Addr vpn, uint8_t asn) const
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{
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// assume not found...
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ArmISA::PTE *retval = NULL;
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PageTable::const_iterator i = lookupTable.find(vpn);
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if (i != lookupTable.end()) {
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while (i->first == vpn) {
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int index = i->second;
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ArmISA::PTE *pte = &table[index];
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/* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */
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Addr Mask = pte->Mask;
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Addr InvMask = ~Mask;
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Addr VPN = pte->VPN;
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// warn("Valid: %d - %d\n",pte->V0,pte->V1);
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if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid)))
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{ // We have a VPN + ASID Match
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retval = pte;
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break;
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}
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++i;
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}
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}
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DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
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retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
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return retval;
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}
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ArmISA::PTE* TLB::getEntry(unsigned Index) const
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{
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// Make sure that Index is valid
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assert(Index<size);
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return &table[Index];
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}
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int TLB::probeEntry(Addr vpn,uint8_t asn) const
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{
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// assume not found...
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ArmISA::PTE *retval = NULL;
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int Ind=-1;
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PageTable::const_iterator i = lookupTable.find(vpn);
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if (i != lookupTable.end()) {
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while (i->first == vpn) {
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int index = i->second;
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ArmISA::PTE *pte = &table[index];
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/* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */
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Addr Mask = pte->Mask;
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Addr InvMask = ~Mask;
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Addr VPN = pte->VPN;
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if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid)))
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{ // We have a VPN + ASID Match
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retval = pte;
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Ind = index;
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break;
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}
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++i;
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}
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}
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DPRINTF(Arm,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
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return Ind;
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}
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Fault inline
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TLB::checkCacheability(RequestPtr &req)
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{
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Addr VAddrUncacheable = 0xA0000000;
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// In ARM, cacheability is controlled by certain bits of the virtual address
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// or by the TLB entry
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if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
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// mark request as uncacheable
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req->setFlags(Request::UNCACHEABLE);
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}
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return NoFault;
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}
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void TLB::insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages)
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{
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smallPages=_smallPages;
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if(Index > size){
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warn("Attempted to write at index (%d) beyond TLB size (%d)",Index,size);
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} else {
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// Update TLB
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DPRINTF(TLB,"TLB[%d]: %x %x %x %x\n",Index,pte.Mask<<11,((pte.VPN << 11) | pte.asid),((pte.PFN0 <<6) | (pte.C0 << 3) | (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
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((pte.PFN1 <<6) | (pte.C1 << 3) | (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
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if(table[Index].V0 == true || table[Index].V1 == true){ // Previous entry is valid
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PageTable::iterator i = lookupTable.find(table[Index].VPN);
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lookupTable.erase(i);
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}
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table[Index]=pte;
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// Update fast lookup table
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lookupTable.insert(make_pair(table[Index].VPN, Index));
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// int TestIndex=probeEntry(pte.VPN,pte.asid);
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// warn("Inserted at: %d, Found at: %d (%x)\n",Index,TestIndex,pte.Mask);
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}
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panic("lookup() not implemented for ARM\n");
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}
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// insert a new TLB entry
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@ -219,11 +115,9 @@ TLB::unserialize(Checkpoint *cp, const string §ion)
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UNSERIALIZE_SCALAR(size);
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UNSERIALIZE_SCALAR(nlu);
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panic("Need to properly unserialize TLB\n");
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for (int i = 0; i < size; i++) {
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table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
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if (table[i].V0 || table[i].V1) {
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lookupTable.insert(make_pair(table[i].VPN, i));
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}
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}
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}
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@ -334,17 +228,6 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
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translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
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}
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ArmISA::PTE &
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TLB::index(bool advance)
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{
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ArmISA::PTE *pte = &table[nlu];
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if (advance)
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nextnlu();
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return *pte;
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}
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ArmISA::TLB *
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ArmTLBParams::create()
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{
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@ -1,7 +1,17 @@
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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||||
*
|
||||
* The license below extends only to copyright in the software and shall
|
||||
* not be construed as granting a license to any other intellectual
|
||||
* property including but not limited to intellectual property relating
|
||||
* to a hardware implementation of the functionality of the software
|
||||
* licensed hereunder. You may use the software subject to the license
|
||||
* terms below provided that you ensure that this notice is replicated
|
||||
* unmodified and in its entirety in all distributions of the software,
|
||||
* modified or unmodified, in source code or in binary form.
|
||||
*
|
||||
* Copyright (c) 2001-2005 The Regents of The University of Michigan
|
||||
* Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
* Copyright (c) 2007-2008 The Florida State University
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -27,9 +37,7 @@
|
|||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Nathan Binkert
|
||||
* Steve Reinhardt
|
||||
* Stephen Hines
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||||
* Authors: Ali Saidi
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*/
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#ifndef __ARCH_ARM_TLB_HH__
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@ -49,41 +57,8 @@
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class ThreadContext;
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/* ARM does not distinguish between a DTLB and an ITLB -> unified TLB
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However, to maintain compatibility with other architectures, we'll
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simply create an ITLB and DTLB that will point to the real TLB */
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namespace ArmISA {
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// WARN: This particular TLB entry is not necessarily conformed to ARM ISA
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struct TlbEntry
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{
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Addr _pageStart;
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TlbEntry() {}
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TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
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void
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updateVaddr(Addr new_vaddr)
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{
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panic("unimplemented");
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}
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Addr pageStart()
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{
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return _pageStart;
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}
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void serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(_pageStart);
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}
|
||||
|
||||
void unserialize(Checkpoint *cp, const std::string §ion)
|
||||
{
|
||||
UNSERIALIZE_SCALAR(_pageStart);
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
class TLB : public BaseTLB
|
||||
{
|
||||
public:
|
||||
|
|
@ -112,6 +87,7 @@ class TLB : public BaseTLB
|
|||
void nextnlu() { if (++nlu >= size) nlu = 0; }
|
||||
ArmISA::PTE *lookup(Addr vpn, uint8_t asn) const;
|
||||
|
||||
// Access Stats
|
||||
mutable Stats::Scalar read_hits;
|
||||
mutable Stats::Scalar read_misses;
|
||||
mutable Stats::Scalar read_acv;
|
||||
|
|
@ -129,26 +105,18 @@ class TLB : public BaseTLB
|
|||
typedef ArmTLBParams Params;
|
||||
TLB(const Params *p);
|
||||
|
||||
int probeEntry(Addr vpn,uint8_t) const;
|
||||
ArmISA::PTE *getEntry(unsigned) const;
|
||||
virtual ~TLB();
|
||||
int smallPages;
|
||||
int getsize() const { return size; }
|
||||
|
||||
ArmISA::PTE &index(bool advance = true);
|
||||
void insert(Addr vaddr, ArmISA::PTE &pte);
|
||||
void insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages);
|
||||
void flushAll();
|
||||
void demapPage(Addr vaddr, uint64_t asn)
|
||||
{
|
||||
panic("demapPage unimplemented.\n");
|
||||
}
|
||||
|
||||
// static helper functions... really
|
||||
static bool validVirtualAddress(Addr vaddr);
|
||||
|
||||
static Fault checkCacheability(RequestPtr &req);
|
||||
|
||||
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
|
||||
void translateTiming(RequestPtr req, ThreadContext *tc,
|
||||
Translation *translation, Mode mode);
|
||||
|
|
|
|||
Loading…
Reference in a new issue