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ARM: Make MPIDR return 0 and ignore writes.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:15 -05:00
parent 49b7088b91
commit fd37095fa6
2 changed files with 6 additions and 3 deletions
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3
src/arch/arm/isa.hh
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@ -155,6 +155,8 @@ namespace ArmISA
mvfr1.vfpHalfPrecision = 1;
miscRegs[MISCREG_MVFR1] = mvfr1;
miscRegs[MISCREG_MPIDR] = 0;
//XXX We need to initialize the rest of the state.
}
@ -296,6 +298,7 @@ namespace ArmISA
case MISCREG_TLBTR:
case MISCREG_MVFR0:
case MISCREG_MVFR1:
case MISCREG_MPIDR:
return;
}
return setMiscRegNoEffect(misc_reg, newVal);

6
src/arch/arm/miscregs.hh
View file

@ -128,10 +128,10 @@ namespace ArmISA
MISCREG_IFSR,
MISCREG_DFAR,
MISCREG_IFAR,
MISCREG_MPIDR,
MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR,
MISCREG_MPIDR,
MISCREG_ID_PFR0,
MISCREG_ID_PFR1,
MISCREG_ID_DFR0,
@ -203,8 +203,8 @@ namespace ArmISA
"itlbiall", "itlbimva", "itlbiasid",
"dtlbiall", "dtlbimva", "dtlbiasid",
"tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
"dfsr", "ifsr", "dfar", "ifar",
"ctr", "tcmtr", "mpidr",
"dfsr", "ifsr", "dfar", "ifar", "mpidr",
"ctr", "tcmtr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",