ARM: Implement and update the DFSR and IFSR registers on faults.
This commit is contained in:
Gabe Black
parent
4491170df6
commit
527b735cfc
4 changed files with 118 additions and 24 deletions
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@ -50,29 +50,29 @@
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namespace ArmISA
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{
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template<> ArmFaultBase::FaultVals ArmFault<Reset>::vals =
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template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals =
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{"reset", 0x00, MODE_SVC, 0, 0, true, true};
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template<> ArmFaultBase::FaultVals ArmFault<UndefinedInstruction>::vals =
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template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals =
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{"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
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template<> ArmFaultBase::FaultVals ArmFault<SupervisorCall>::vals =
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template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals =
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{"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
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template<> ArmFaultBase::FaultVals ArmFault<PrefetchAbort>::vals =
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template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals =
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{"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
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template<> ArmFaultBase::FaultVals ArmFault<DataAbort>::vals =
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template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals =
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{"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
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template<> ArmFaultBase::FaultVals ArmFault<Interrupt>::vals =
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template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals =
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{"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
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template<> ArmFaultBase::FaultVals ArmFault<FastInterrupt>::vals =
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template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals =
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{"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
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Addr
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ArmFaultBase::getVector(ThreadContext *tc)
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ArmFault::getVector(ThreadContext *tc)
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{
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// ARM ARM B1-3
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@ -91,7 +91,7 @@ ArmFaultBase::getVector(ThreadContext *tc)
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#if FULL_SYSTEM
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void
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ArmFaultBase::invoke(ThreadContext *tc)
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ArmFault::invoke(ThreadContext *tc)
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{
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// ARM ARM B1.6.3
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FaultBase::invoke(tc);
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@ -185,6 +185,24 @@ SupervisorCall::invoke(ThreadContext *tc)
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#endif // FULL_SYSTEM
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template<class T>
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void
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AbortFault<T>::invoke(ThreadContext *tc)
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{
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ArmFaultVals<T>::invoke(tc);
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FSR fsr = 0;
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fsr.fsLow = bits(status, 3, 0);
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fsr.fsHigh = bits(status, 4);
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fsr.domain = domain;
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fsr.wnr = (write ? 1 : 0);
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fsr.ext = 0;
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tc->setMiscReg(T::FsrIndex, fsr);
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tc->setMiscReg(T::FarIndex, faultAddr);
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}
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template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc);
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template void AbortFault<DataAbort>::invoke(ThreadContext *tc);
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// return via SUBS pc, lr, xxx; rfe, movs, ldm
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@ -45,6 +45,7 @@
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#ifndef __ARM_FAULTS_HH__
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#define __ARM_FAULTS_HH__
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#include "arch/arm/miscregs.hh"
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#include "arch/arm/types.hh"
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#include "config/full_system.hh"
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#include "sim/faults.hh"
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@ -55,12 +56,37 @@ namespace ArmISA
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{
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typedef const Addr FaultOffset;
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class ArmFaultBase : public FaultBase
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class ArmFault : public FaultBase
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{
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protected:
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Addr getVector(ThreadContext *tc);
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public:
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enum StatusEncoding
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{
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// Fault Status register encodings
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// ARM ARM B3.9.4
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AlignmentFault = 0x1,
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DebugEvent = 0x2,
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AccessFlag0 = 0x3,
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InstructionCacheMaintenance = 0x4,
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Translation0 = 0x5,
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AccessFlag1 = 0x6,
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Translation1 = 0x7,
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SynchronousExternalAbort0 = 0x8,
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Domain0 = 0x9,
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Domain1 = 0xb,
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TranslationTableWalk0 = 0xc,
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Permission0 = 0xd,
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SynchronousExternalAbort1 = 0xe,
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Permission1 = 0xf,
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AsynchronousExternalAbort = 0x16,
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MemoryAccessAsynchronousParityError = 0x18,
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MemoryAccessSynchronousParityError = 0x19,
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TranslationTableWalk1 = 0x1c,
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SynchronousParityError = 0x1e
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};
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struct FaultVals
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{
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const FaultName name;
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@ -86,7 +112,7 @@ class ArmFaultBase : public FaultBase
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};
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template<typename T>
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class ArmFault : public ArmFaultBase
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class ArmFaultVals : public ArmFault
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{
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protected:
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static FaultVals vals;
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@ -103,9 +129,9 @@ class ArmFault : public ArmFaultBase
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};
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class Reset : public ArmFault<Reset> {};
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class Reset : public ArmFaultVals<Reset> {};
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class UndefinedInstruction : public ArmFault<UndefinedInstruction>
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class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
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{
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#if !FULL_SYSTEM
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protected:
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@ -125,7 +151,7 @@ class UndefinedInstruction : public ArmFault<UndefinedInstruction>
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#endif
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};
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class SupervisorCall : public ArmFault<SupervisorCall>
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class SupervisorCall : public ArmFaultVals<SupervisorCall>
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{
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#if !FULL_SYSTEM
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protected:
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@ -138,10 +164,50 @@ class SupervisorCall : public ArmFault<SupervisorCall>
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void invoke(ThreadContext *tc);
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#endif
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};
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class PrefetchAbort : public ArmFault<PrefetchAbort> {};
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class DataAbort : public ArmFault<DataAbort> {};
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class Interrupt : public ArmFault<Interrupt> {};
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class FastInterrupt : public ArmFault<FastInterrupt> {};
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template <class T>
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class AbortFault : public ArmFaultVals<T>
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{
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protected:
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Addr faultAddr;
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bool write;
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uint8_t domain;
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uint8_t status;
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public:
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AbortFault(Addr _faultAddr, bool _write,
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uint8_t _domain, uint8_t _status) :
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faultAddr(_faultAddr), write(_write),
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domain(_domain), status(_status)
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{}
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void invoke(ThreadContext *tc);
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};
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class PrefetchAbort : public AbortFault<PrefetchAbort>
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{
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public:
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static const MiscRegIndex FsrIndex = MISCREG_IFSR;
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static const MiscRegIndex FarIndex = MISCREG_IFAR;
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PrefetchAbort(Addr _addr, uint8_t _status) :
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AbortFault<PrefetchAbort>(_addr, false, 0, _status)
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{}
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};
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class DataAbort : public AbortFault<DataAbort>
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{
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public:
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static const MiscRegIndex FsrIndex = MISCREG_DFSR;
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static const MiscRegIndex FarIndex = MISCREG_DFAR;
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DataAbort(Addr _addr, bool _write, uint8_t _domain, uint8_t _status) :
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AbortFault<DataAbort>(_addr, _write, _domain, _status)
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{}
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};
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class Interrupt : public ArmFaultVals<Interrupt> {};
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class FastInterrupt : public ArmFaultVals<FastInterrupt> {};
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} // ArmISA namespace
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@ -124,6 +124,10 @@ namespace ArmISA
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MISCREG_TLBIMVA,
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MISCREG_TLBIASID,
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MISCREG_TLBIMVAA,
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MISCREG_DFSR,
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MISCREG_IFSR,
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MISCREG_DFAR,
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MISCREG_IFAR,
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MISCREG_CP15_UNIMP_START,
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MISCREG_CTR = MISCREG_CP15_UNIMP_START,
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MISCREG_TCMTR,
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@ -145,12 +149,8 @@ namespace ArmISA
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MISCREG_PAR,
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MISCREG_AIDR,
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MISCREG_ACTLR,
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MISCREG_DFSR,
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MISCREG_IFSR,
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MISCREG_ADFSR,
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MISCREG_AIFSR,
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MISCREG_DFAR,
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MISCREG_IFAR,
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MISCREG_DCIMVAC,
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MISCREG_DCISW,
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MISCREG_MCCSW,
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@ -203,12 +203,13 @@ namespace ArmISA
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"itlbiall", "itlbimva", "itlbiasid",
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"dtlbiall", "dtlbimva", "dtlbiasid",
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"tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
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"dfsr", "ifsr", "dfar", "ifar",
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"ctr", "tcmtr", "mpidr",
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"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
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"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
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"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
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"par", "aidr", "actlr",
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"dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
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"adfsr", "aifsr",
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"dcimvac", "dcisw", "mccsw",
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"dccmvau",
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"scr", "sder", "nsacr", "ttbcr",
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@ -285,6 +286,14 @@ namespace ArmISA
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Bitfield<30> d32dis;
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Bitfield<31> asedis;
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EndBitUnion(CPACR)
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BitUnion32(FSR)
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Bitfield<3, 0> fsLow;
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Bitfield<7, 4> domain;
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Bitfield<10> fsHigh;
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Bitfield<11> wnr;
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Bitfield<12> ext;
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EndBitUnion(FSR)
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};
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#endif // __ARCH_ARM_MISCREGS_HH__
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@ -299,7 +299,8 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
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if (sctlr.a || (flags & AllowUnaligned) == 0) {
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if ((vaddr & flags & AlignmentMask) != 0) {
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return new DataAbort;
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return new DataAbort(vaddr, (mode == Write), 0,
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ArmFault::AlignmentFault);
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}
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}
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}
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