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ARM: Undef instruction on invalid user CP15 access

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This commit is contained in:
Ali Saidi 2010-06-02 12:58:13 -05:00
parent 2e4ddbd234
commit 65a5177b53
1 changed files with 24 additions and 2 deletions
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26
src/arch/arm/isa/insts/misc.isa
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@ -501,15 +501,37 @@ let {{
decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
exec_output += PredOpExecute.subst(bfiIop)
mrc15code = '''
CPSR cpsr = Cpsr;
if (cpsr.mode == MODE_USER)
#if FULL_SYSTEM
return new UndefinedInstruction;
#else
return new UndefinedInstruction(false, mnemonic);
#endif
Dest = MiscOp1;
'''
mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
{ "code": "Dest = MiscOp1;",
{ "code": mrc15code,
"predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(mrc15Iop)
decoder_output += RegRegOpConstructor.subst(mrc15Iop)
exec_output += PredOpExecute.subst(mrc15Iop)
mcr15code = '''
CPSR cpsr = Cpsr;
if (cpsr.mode == MODE_USER)
#if FULL_SYSTEM
return new UndefinedInstruction;
#else
return new UndefinedInstruction(false, mnemonic);
#endif
MiscDest = Op1;
'''
mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
{ "code": "MiscDest = Op1;",
{ "code": mcr15code,
"predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(mcr15Iop)
decoder_output += RegRegOpConstructor.subst(mcr15Iop)