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ARM: Implement VCVT between double and single width FP.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:14 -05:00
parent a430f749ce
commit 41012d2418
2 changed files with 34 additions and 2 deletions
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11
src/arch/arm/isa/formats/fp.isa
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@ -616,8 +616,15 @@ let {{
return new WarnUnimplemented("vcmp, vcmpe", machInst);
case 0x7:
if (opc3 == 0x3) {
// Between double and single precision.
return new WarnUnimplemented("vcvt", machInst);
if (single) {
vm = (IntRegIndex)(bits(machInst, 5) |
(bits(machInst, 3, 0) << 1));
return new VcvtFpSFpD(machInst, vd, vm);
} else {
vd = (IntRegIndex)(bits(machInst, 22) |
(bits(machInst, 15, 12) << 1));
return new VcvtFpDFpS(machInst, vd, vm);
}
}
break;
case 0x8:

25
src/arch/arm/isa/insts/fp.isa
View file

@ -678,4 +678,29 @@ let {{
header_output += RegRegOpDeclare.subst(vcvtFpSIntDIop);
decoder_output += RegRegOpConstructor.subst(vcvtFpSIntDIop);
exec_output += PredOpExecute.subst(vcvtFpSIntDIop);
vcvtFpSFpDCode = '''
IntDoubleUnion cDest;
cDest.fp = FpOp1;
FpDestP0.uw = cDest.bits;
FpDestP1.uw = cDest.bits >> 32;
'''
vcvtFpSFpDIop = InstObjParams("vcvt", "VcvtFpSFpD", "RegRegOp",
{ "code": vcvtFpSFpDCode,
"predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(vcvtFpSFpDIop);
decoder_output += RegRegOpConstructor.subst(vcvtFpSFpDIop);
exec_output += PredOpExecute.subst(vcvtFpSFpDIop);
vcvtFpDFpSCode = '''
IntDoubleUnion cOp1;
cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
FpDest = cOp1.fp;
'''
vcvtFpDFpSIop = InstObjParams("vcvt", "VcvtFpDFpS", "RegRegOp",
{ "code": vcvtFpDFpSCode,
"predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(vcvtFpDFpSIop);
decoder_output += RegRegOpConstructor.subst(vcvtFpDFpSIop);
exec_output += PredOpExecute.subst(vcvtFpDFpSIop);
}};