ARM: Move Miscreg functions out of isa.hh
This commit is contained in:
Ali Saidi
parent
cb9936cfde
commit
7de7ea3b22
4 changed files with 287 additions and 229 deletions
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@ -55,6 +55,7 @@ if env['TARGET_ISA'] == 'arm':
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Source('insts/pred_inst.cc')
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Source('insts/static_inst.cc')
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Source('insts/vfp.cc')
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Source('isa.cc')
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Source('miscregs.cc')
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Source('nativetrace.cc')
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Source('tlb.cc')
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280
src/arch/arm/isa.cc
Normal file
280
src/arch/arm/isa.cc
Normal file
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@ -0,0 +1,280 @@
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Ali Saidi
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*/
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#include "arch/arm/isa.hh"
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namespace ArmISA
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{
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MiscReg
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ISA::readMiscRegNoEffect(int misc_reg)
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{
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assert(misc_reg < NumMiscRegs);
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if (misc_reg == MISCREG_SPSR) {
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CPSR cpsr = miscRegs[MISCREG_CPSR];
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switch (cpsr.mode) {
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case MODE_USER:
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return miscRegs[MISCREG_SPSR];
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case MODE_FIQ:
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return miscRegs[MISCREG_SPSR_FIQ];
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case MODE_IRQ:
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return miscRegs[MISCREG_SPSR_IRQ];
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case MODE_SVC:
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return miscRegs[MISCREG_SPSR_SVC];
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case MODE_MON:
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return miscRegs[MISCREG_SPSR_MON];
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case MODE_ABORT:
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return miscRegs[MISCREG_SPSR_ABT];
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case MODE_UNDEFINED:
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return miscRegs[MISCREG_SPSR_UND];
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default:
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return miscRegs[MISCREG_SPSR];
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}
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}
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return miscRegs[misc_reg];
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}
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MiscReg
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ISA::readMiscReg(int misc_reg, ThreadContext *tc)
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{
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if (misc_reg == MISCREG_CPSR) {
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CPSR cpsr = miscRegs[misc_reg];
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Addr pc = tc->readPC();
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if (pc & (ULL(1) << PcJBitShift))
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cpsr.j = 1;
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else
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cpsr.j = 0;
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if (pc & (ULL(1) << PcTBitShift))
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cpsr.t = 1;
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else
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cpsr.t = 0;
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return cpsr;
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}
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if (misc_reg >= MISCREG_CP15_UNIMP_START &&
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misc_reg < MISCREG_CP15_END) {
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panic("Unimplemented CP15 register %s read.\n",
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miscRegName[misc_reg]);
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}
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switch (misc_reg) {
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case MISCREG_CLIDR:
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warn("The clidr register always reports 0 caches.\n");
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break;
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case MISCREG_CCSIDR:
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warn("The ccsidr register isn't implemented and "
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"always reads as 0.\n");
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break;
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case MISCREG_ID_PFR0:
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return 0x1031; // ThumbEE | !Jazelle | Thumb | ARM
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}
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return readMiscRegNoEffect(misc_reg);
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}
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void
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ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
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{
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assert(misc_reg < NumMiscRegs);
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if (misc_reg == MISCREG_SPSR) {
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CPSR cpsr = miscRegs[MISCREG_CPSR];
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switch (cpsr.mode) {
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case MODE_USER:
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miscRegs[MISCREG_SPSR] = val;
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return;
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case MODE_FIQ:
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miscRegs[MISCREG_SPSR_FIQ] = val;
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return;
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case MODE_IRQ:
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miscRegs[MISCREG_SPSR_IRQ] = val;
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return;
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case MODE_SVC:
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miscRegs[MISCREG_SPSR_SVC] = val;
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return;
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case MODE_MON:
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miscRegs[MISCREG_SPSR_MON] = val;
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return;
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case MODE_ABORT:
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miscRegs[MISCREG_SPSR_ABT] = val;
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return;
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case MODE_UNDEFINED:
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miscRegs[MISCREG_SPSR_UND] = val;
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return;
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default:
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miscRegs[MISCREG_SPSR] = val;
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return;
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}
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}
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miscRegs[misc_reg] = val;
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}
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void
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ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
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{
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MiscReg newVal = val;
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if (misc_reg == MISCREG_CPSR) {
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updateRegMap(val);
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CPSR cpsr = val;
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DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
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cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
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Addr npc = tc->readNextPC() & ~PcModeMask;
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if (cpsr.j)
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npc = npc | (ULL(1) << PcJBitShift);
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if (cpsr.t)
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npc = npc | (ULL(1) << PcTBitShift);
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tc->setNextPC(npc);
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}
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if (misc_reg >= MISCREG_CP15_UNIMP_START &&
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misc_reg < MISCREG_CP15_END) {
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panic("Unimplemented CP15 register %s wrote with %#x.\n",
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miscRegName[misc_reg], val);
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}
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switch (misc_reg) {
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case MISCREG_CPACR:
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{
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CPACR newCpacr = 0;
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CPACR valCpacr = val;
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newCpacr.cp10 = valCpacr.cp10;
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newCpacr.cp11 = valCpacr.cp11;
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if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
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panic("Disabling coprocessors isn't implemented.\n");
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}
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newVal = newCpacr;
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}
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break;
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case MISCREG_CSSELR:
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warn("The csselr register isn't implemented.\n");
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break;
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case MISCREG_FPSCR:
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{
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const uint32_t ones = (uint32_t)(-1);
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FPSCR fpscrMask = 0;
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fpscrMask.ioc = ones;
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fpscrMask.dzc = ones;
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fpscrMask.ofc = ones;
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fpscrMask.ufc = ones;
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fpscrMask.ixc = ones;
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fpscrMask.idc = ones;
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fpscrMask.len = ones;
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fpscrMask.stride = ones;
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fpscrMask.rMode = ones;
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fpscrMask.fz = ones;
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fpscrMask.dn = ones;
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fpscrMask.ahp = ones;
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fpscrMask.qc = ones;
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fpscrMask.v = ones;
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fpscrMask.c = ones;
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fpscrMask.z = ones;
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fpscrMask.n = ones;
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newVal = (newVal & (uint32_t)fpscrMask) |
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(miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
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}
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break;
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case MISCREG_FPEXC:
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{
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const uint32_t fpexcMask = 0x60000000;
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newVal = (newVal & fpexcMask) |
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(miscRegs[MISCREG_FPEXC] & ~fpexcMask);
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}
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break;
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case MISCREG_SCTLR:
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{
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SCTLR sctlr = miscRegs[MISCREG_SCTLR];
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SCTLR new_sctlr = newVal;
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new_sctlr.nmfi = (bool)sctlr.nmfi;
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miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
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return;
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}
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case MISCREG_TLBTR:
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case MISCREG_MVFR0:
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case MISCREG_MVFR1:
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case MISCREG_MPIDR:
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case MISCREG_FPSID:
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return;
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case MISCREG_TLBIALLIS:
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case MISCREG_TLBIALL:
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warn("Need to flush all TLBs in MP\n");
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tc->getITBPtr()->flushAll();
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tc->getDTBPtr()->flushAll();
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return;
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case MISCREG_ITLBIALL:
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tc->getITBPtr()->flushAll();
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return;
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case MISCREG_DTLBIALL:
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tc->getDTBPtr()->flushAll();
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return;
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case MISCREG_TLBIMVAIS:
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case MISCREG_TLBIMVA:
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warn("Need to flush all TLBs in MP\n");
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tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
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bits(newVal, 7,0));
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tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
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bits(newVal, 7,0));
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return;
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case MISCREG_TLBIASIDIS:
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case MISCREG_TLBIASID:
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warn("Need to flush all TLBs in MP\n");
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tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
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tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
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return;
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case MISCREG_TLBIMVAAIS:
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case MISCREG_TLBIMVAA:
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warn("Need to flush all TLBs in MP\n");
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tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
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tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
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return;
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case MISCREG_ITLBIMVA:
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tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
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bits(newVal, 7,0));
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return;
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case MISCREG_DTLBIMVA:
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tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
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bits(newVal, 7,0));
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return;
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case MISCREG_ITLBIASID:
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tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
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return;
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case MISCREG_DTLBIASID:
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tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
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return;
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}
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setMiscRegNoEffect(misc_reg, newVal);
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}
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}
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@ -167,238 +167,13 @@ namespace ArmISA
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//XXX We need to initialize the rest of the state.
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}
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MiscReg
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readMiscRegNoEffect(int misc_reg)
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{
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assert(misc_reg < NumMiscRegs);
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if (misc_reg == MISCREG_SPSR) {
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CPSR cpsr = miscRegs[MISCREG_CPSR];
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switch (cpsr.mode) {
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case MODE_USER:
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return miscRegs[MISCREG_SPSR];
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case MODE_FIQ:
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return miscRegs[MISCREG_SPSR_FIQ];
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case MODE_IRQ:
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return miscRegs[MISCREG_SPSR_IRQ];
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case MODE_SVC:
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return miscRegs[MISCREG_SPSR_SVC];
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case MODE_MON:
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return miscRegs[MISCREG_SPSR_MON];
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case MODE_ABORT:
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return miscRegs[MISCREG_SPSR_ABT];
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case MODE_UNDEFINED:
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return miscRegs[MISCREG_SPSR_UND];
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default:
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return miscRegs[MISCREG_SPSR];
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}
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}
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return miscRegs[misc_reg];
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}
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MiscReg readMiscRegNoEffect(int misc_reg);
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MiscReg
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readMiscReg(int misc_reg, ThreadContext *tc)
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{
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if (misc_reg == MISCREG_CPSR) {
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CPSR cpsr = miscRegs[misc_reg];
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Addr pc = tc->readPC();
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if (pc & (ULL(1) << PcJBitShift))
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cpsr.j = 1;
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else
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cpsr.j = 0;
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if (pc & (ULL(1) << PcTBitShift))
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cpsr.t = 1;
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else
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cpsr.t = 0;
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return cpsr;
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}
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if (misc_reg >= MISCREG_CP15_UNIMP_START &&
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misc_reg < MISCREG_CP15_END) {
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panic("Unimplemented CP15 register %s read.\n",
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miscRegName[misc_reg]);
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}
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switch (misc_reg) {
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case MISCREG_CLIDR:
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warn("The clidr register always reports 0 caches.\n");
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break;
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case MISCREG_CCSIDR:
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warn("The ccsidr register isn't implemented and "
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"always reads as 0.\n");
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break;
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case MISCREG_ID_PFR0:
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return 0x1031; // ThumbEE | !Jazelle | Thumb | ARM
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}
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return readMiscRegNoEffect(misc_reg);
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}
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MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
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void
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setMiscRegNoEffect(int misc_reg, const MiscReg &val)
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{
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assert(misc_reg < NumMiscRegs);
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if (misc_reg == MISCREG_SPSR) {
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CPSR cpsr = miscRegs[MISCREG_CPSR];
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switch (cpsr.mode) {
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case MODE_USER:
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miscRegs[MISCREG_SPSR] = val;
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return;
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case MODE_FIQ:
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miscRegs[MISCREG_SPSR_FIQ] = val;
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return;
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case MODE_IRQ:
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miscRegs[MISCREG_SPSR_IRQ] = val;
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return;
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case MODE_SVC:
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miscRegs[MISCREG_SPSR_SVC] = val;
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return;
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case MODE_MON:
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miscRegs[MISCREG_SPSR_MON] = val;
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return;
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case MODE_ABORT:
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miscRegs[MISCREG_SPSR_ABT] = val;
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return;
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case MODE_UNDEFINED:
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miscRegs[MISCREG_SPSR_UND] = val;
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return;
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default:
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miscRegs[MISCREG_SPSR] = val;
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return;
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}
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}
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miscRegs[misc_reg] = val;
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}
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void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
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void
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setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
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{
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MiscReg newVal = val;
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if (misc_reg == MISCREG_CPSR) {
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updateRegMap(val);
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CPSR cpsr = val;
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DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
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cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
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Addr npc = tc->readNextPC() & ~PcModeMask;
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if (cpsr.j)
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npc = npc | (ULL(1) << PcJBitShift);
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if (cpsr.t)
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npc = npc | (ULL(1) << PcTBitShift);
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tc->setNextPC(npc);
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}
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if (misc_reg >= MISCREG_CP15_UNIMP_START &&
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misc_reg < MISCREG_CP15_END) {
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panic("Unimplemented CP15 register %s wrote with %#x.\n",
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miscRegName[misc_reg], val);
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}
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switch (misc_reg) {
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case MISCREG_CPACR:
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{
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CPACR newCpacr = 0;
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CPACR valCpacr = val;
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newCpacr.cp10 = valCpacr.cp10;
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newCpacr.cp11 = valCpacr.cp11;
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if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
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panic("Disabling coprocessors isn't implemented.\n");
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}
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newVal = newCpacr;
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}
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break;
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case MISCREG_CSSELR:
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warn("The csselr register isn't implemented.\n");
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break;
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case MISCREG_FPSCR:
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{
|
||||
const uint32_t ones = (uint32_t)(-1);
|
||||
FPSCR fpscrMask = 0;
|
||||
fpscrMask.ioc = ones;
|
||||
fpscrMask.dzc = ones;
|
||||
fpscrMask.ofc = ones;
|
||||
fpscrMask.ufc = ones;
|
||||
fpscrMask.ixc = ones;
|
||||
fpscrMask.idc = ones;
|
||||
fpscrMask.len = ones;
|
||||
fpscrMask.stride = ones;
|
||||
fpscrMask.rMode = ones;
|
||||
fpscrMask.fz = ones;
|
||||
fpscrMask.dn = ones;
|
||||
fpscrMask.ahp = ones;
|
||||
fpscrMask.qc = ones;
|
||||
fpscrMask.v = ones;
|
||||
fpscrMask.c = ones;
|
||||
fpscrMask.z = ones;
|
||||
fpscrMask.n = ones;
|
||||
newVal = (newVal & (uint32_t)fpscrMask) |
|
||||
(miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
|
||||
}
|
||||
break;
|
||||
case MISCREG_FPEXC:
|
||||
{
|
||||
const uint32_t fpexcMask = 0x60000000;
|
||||
newVal = (newVal & fpexcMask) |
|
||||
(miscRegs[MISCREG_FPEXC] & ~fpexcMask);
|
||||
}
|
||||
break;
|
||||
case MISCREG_SCTLR:
|
||||
{
|
||||
SCTLR sctlr = miscRegs[MISCREG_SCTLR];
|
||||
SCTLR new_sctlr = newVal;
|
||||
new_sctlr.nmfi = (bool)sctlr.nmfi;
|
||||
miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr;
|
||||
return;
|
||||
}
|
||||
case MISCREG_TLBTR:
|
||||
case MISCREG_MVFR0:
|
||||
case MISCREG_MVFR1:
|
||||
case MISCREG_MPIDR:
|
||||
case MISCREG_FPSID:
|
||||
return;
|
||||
case MISCREG_TLBIALLIS:
|
||||
case MISCREG_TLBIALL:
|
||||
warn("Need to flush all TLBs in MP\n");
|
||||
tc->getITBPtr()->flushAll();
|
||||
tc->getDTBPtr()->flushAll();
|
||||
return;
|
||||
case MISCREG_ITLBIALL:
|
||||
tc->getITBPtr()->flushAll();
|
||||
return;
|
||||
case MISCREG_DTLBIALL:
|
||||
tc->getDTBPtr()->flushAll();
|
||||
return;
|
||||
case MISCREG_TLBIMVAIS:
|
||||
case MISCREG_TLBIMVA:
|
||||
warn("Need to flush all TLBs in MP\n");
|
||||
tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
|
||||
bits(newVal, 7,0));
|
||||
tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
|
||||
bits(newVal, 7,0));
|
||||
return;
|
||||
case MISCREG_TLBIASIDIS:
|
||||
case MISCREG_TLBIASID:
|
||||
warn("Need to flush all TLBs in MP\n");
|
||||
tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
|
||||
tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
|
||||
return;
|
||||
case MISCREG_TLBIMVAAIS:
|
||||
case MISCREG_TLBIMVAA:
|
||||
warn("Need to flush all TLBs in MP\n");
|
||||
tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
|
||||
tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
|
||||
return;
|
||||
case MISCREG_ITLBIMVA:
|
||||
tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
|
||||
bits(newVal, 7,0));
|
||||
return;
|
||||
case MISCREG_DTLBIMVA:
|
||||
tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
|
||||
bits(newVal, 7,0));
|
||||
return;
|
||||
case MISCREG_ITLBIASID:
|
||||
tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
|
||||
return;
|
||||
case MISCREG_DTLBIASID:
|
||||
tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
|
||||
return;
|
||||
}
|
||||
setMiscRegNoEffect(misc_reg, newVal);
|
||||
}
|
||||
void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
|
||||
|
||||
int
|
||||
flattenIntIndex(int reg)
|
||||
|
|
|
|||
|
|
@ -35,8 +35,10 @@
|
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Gabe Black
|
||||
* Ali Saidi
|
||||
*/
|
||||
|
||||
#include "arch/arm/isa.hh"
|
||||
#include "arch/arm/miscregs.hh"
|
||||
#include "base/misc.hh"
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue