b6e2f5d33f
This change moves the writeback of load multiple instructions to the beginning of the macroop. That way, the MicroLdrRetUop that changes the mode will necessarily happen later, ensuring the writeback happens in the original mode. The actual value in the base register if it also shows up in the register list is undefined, so it's fine if it gets clobbered by one of the loads. For stores where the base register is the lowest numbered in the register list, the original value should be written back. That means stores can't write back at the beginning, but the mode changing problem doesn't affect them so they can continue to write back at the end. |
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| .. | ||
| alpha | ||
| arm | ||
| mips | ||
| power | ||
| sparc | ||
| x86 | ||
| isa_parser.py | ||
| micro_asm.py | ||
| micro_asm_test.py | ||
| SConscript | ||