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ARM: Implement the VFP version of vdiv and vsqrt.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:14 -05:00
parent cc665240a4
commit 90d70a22cb
2 changed files with 89 additions and 2 deletions
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36
src/arch/arm/isa/formats/fp.isa
View file

@ -552,7 +552,25 @@ let {{
}
case 0x8:
if ((opc3 & 0x1) == 0) {
return new WarnUnimplemented("vdiv", machInst);
uint32_t vd;
uint32_t vm;
uint32_t vn;
if (bits(machInst, 8) == 0) {
vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
return new VdivS(machInst, (IntRegIndex)vd,
(IntRegIndex)vn, (IntRegIndex)vm);
} else {
vd = (bits(machInst, 22) << 5) |
(bits(machInst, 15, 12) << 1);
vm = (bits(machInst, 5) << 5) |
(bits(machInst, 3, 0) << 1);
vn = (bits(machInst, 7) << 5) |
(bits(machInst, 19, 16) << 1);
return new VdivD(machInst, (IntRegIndex)vd,
(IntRegIndex)vn, (IntRegIndex)vm);
}
}
break;
case 0xb:
@ -624,7 +642,21 @@ let {{
(IntRegIndex)vd, (IntRegIndex)vm);
}
} else {
return new WarnUnimplemented("vsqrt", machInst);
uint32_t vd;
uint32_t vm;
if (bits(machInst, 8) == 0) {
vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
return new VsqrtS(machInst,
(IntRegIndex)vd, (IntRegIndex)vm);
} else {
vd = (bits(machInst, 22) << 5) |
(bits(machInst, 15, 12) << 1);
vm = (bits(machInst, 5) << 5) |
(bits(machInst, 3, 0) << 1);
return new VsqrtD(machInst,
(IntRegIndex)vd, (IntRegIndex)vm);
}
}
case 0x2:
case 0x3:

55
src/arch/arm/isa/insts/fp.isa
View file

@ -356,4 +356,59 @@ let {{
header_output += RegRegRegOpDeclare.subst(vsubDIop);
decoder_output += RegRegRegOpConstructor.subst(vsubDIop);
exec_output += PredOpExecute.subst(vsubDIop);
vdivSCode = '''
FpDest = FpOp1 / FpOp2;
'''
vdivSIop = InstObjParams("vdivs", "VdivS", "RegRegRegOp",
{ "code": vdivSCode,
"predicate_test": predicateTest }, [])
header_output += RegRegRegOpDeclare.subst(vdivSIop);
decoder_output += RegRegRegOpConstructor.subst(vdivSIop);
exec_output += PredOpExecute.subst(vdivSIop);
vdivDCode = '''
IntDoubleUnion cOp1, cOp2, cDest;
cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
cDest.fp = cOp1.fp / cOp2.fp;
FpDestP0.uw = cDest.bits;
FpDestP1.uw = cDest.bits >> 32;
'''
vdivDIop = InstObjParams("vdivd", "VdivD", "RegRegRegOp",
{ "code": vdivDCode,
"predicate_test": predicateTest }, [])
header_output += RegRegRegOpDeclare.subst(vdivDIop);
decoder_output += RegRegRegOpConstructor.subst(vdivDIop);
exec_output += PredOpExecute.subst(vdivDIop);
vsqrtSCode = '''
FpDest = sqrtf(FpOp1);
if (FpOp1 < 0) {
FpDest = NAN;
}
'''
vsqrtSIop = InstObjParams("vsqrts", "VsqrtS", "RegRegOp",
{ "code": vsqrtSCode,
"predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(vsqrtSIop);
decoder_output += RegRegOpConstructor.subst(vsqrtSIop);
exec_output += PredOpExecute.subst(vsqrtSIop);
vsqrtDCode = '''
IntDoubleUnion cOp1, cDest;
cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
cDest.fp = sqrt(cOp1.fp);
if (cOp1.fp < 0) {
cDest.fp = NAN;
}
FpDestP0.uw = cDest.bits;
FpDestP1.uw = cDest.bits >> 32;
'''
vsqrtDIop = InstObjParams("vsqrtd", "VsqrtD", "RegRegOp",
{ "code": vsqrtDCode,
"predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(vsqrtDIop);
decoder_output += RegRegOpConstructor.subst(vsqrtDIop);
exec_output += PredOpExecute.subst(vsqrtDIop);
}};