ARM: Define versions of MSR and MRS outside the decoder.
This commit is contained in:
Gabe Black
parent
f61bb9adb9
commit
f0811eb208
7 changed files with 409 additions and 0 deletions
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@ -51,6 +51,7 @@ if env['TARGET_ISA'] == 'arm':
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Source('insts/branch.cc')
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Source('insts/macromem.cc')
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Source('insts/mem.cc')
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Source('insts/misc.cc')
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Source('insts/pred_inst.cc')
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Source('insts/static_inst.cc')
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Source('nativetrace.cc')
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144
src/arch/arm/insts/misc.cc
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144
src/arch/arm/insts/misc.cc
Normal file
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@ -0,0 +1,144 @@
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/arm/insts/misc.hh"
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std::string
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MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss);
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printReg(ss, dest);
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ss << ", ";
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bool foundPsr = false;
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for (unsigned i = 0; i < numSrcRegs(); i++) {
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int idx = srcRegIdx(i);
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if (idx < Ctrl_Base_DepTag) {
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continue;
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}
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idx -= Ctrl_Base_DepTag;
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if (idx == MISCREG_CPSR) {
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ss << "cpsr";
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foundPsr = true;
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break;
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}
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if (idx == MISCREG_SPSR) {
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ss << "spsr";
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foundPsr = true;
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break;
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}
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}
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if (!foundPsr) {
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ss << "????";
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}
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return ss.str();
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}
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void
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MsrBase::printMsrBase(std::ostream &os) const
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{
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printMnemonic(os);
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bool apsr = false;
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bool foundPsr = false;
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for (unsigned i = 0; i < numDestRegs(); i++) {
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int idx = destRegIdx(i);
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if (idx < Ctrl_Base_DepTag) {
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continue;
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}
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idx -= Ctrl_Base_DepTag;
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if (idx == MISCREG_CPSR) {
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os << "cpsr_";
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foundPsr = true;
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break;
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}
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if (idx == MISCREG_SPSR) {
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if (bits(byteMask, 1, 0)) {
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os << "spsr_";
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} else {
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os << "apsr_";
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apsr = true;
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}
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foundPsr = true;
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break;
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}
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}
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if (!foundPsr) {
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os << "????";
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return;
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}
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if (bits(byteMask, 3)) {
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if (apsr) {
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os << "nzcvq";
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} else {
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os << "f";
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}
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}
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if (bits(byteMask, 2)) {
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if (apsr) {
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os << "g";
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} else {
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os << "s";
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}
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}
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if (bits(byteMask, 1)) {
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os << "x";
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}
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if (bits(byteMask, 0)) {
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os << "c";
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}
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}
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std::string
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MsrImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMsrBase(ss);
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ccprintf(ss, ", #%#x", imm);
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return ss.str();
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}
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std::string
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MsrRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMsrBase(ss);
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ss << ", ";
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printReg(ss, op1);
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return ss.str();
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}
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97
src/arch/arm/insts/misc.hh
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97
src/arch/arm/insts/misc.hh
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@ -0,0 +1,97 @@
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ARM_INSTS_MISC_HH__
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#define __ARCH_ARM_INSTS_MISC_HH__
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#include "arch/arm/insts/pred_inst.hh"
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class MrsOp : public PredOp
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{
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protected:
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IntRegIndex dest;
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MrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest) :
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PredOp(mnem, _machInst, __opClass), dest(_dest)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class MsrBase : public PredOp
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{
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protected:
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uint8_t byteMask;
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MsrBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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uint8_t _byteMask) :
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PredOp(mnem, _machInst, __opClass), byteMask(_byteMask)
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{}
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void printMsrBase(std::ostream &os) const;
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};
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class MsrImmOp : public MsrBase
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{
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protected:
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uint32_t imm;
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MsrImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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uint32_t _imm, uint8_t _byteMask) :
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MsrBase(mnem, _machInst, __opClass, _byteMask), imm(_imm)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class MsrRegOp : public MsrBase
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{
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protected:
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IntRegIndex op1;
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MsrRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _op1, uint8_t _byteMask) :
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MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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#endif
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@ -52,6 +52,7 @@ output header {{
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#include "arch/arm/insts/branch.hh"
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#include "arch/arm/insts/macromem.hh"
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#include "arch/arm/insts/mem.hh"
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#include "arch/arm/insts/misc.hh"
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#include "arch/arm/insts/mult.hh"
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#include "arch/arm/insts/pred_inst.hh"
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#include "arch/arm/insts/static_inst.hh"
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@ -55,3 +55,66 @@ let {{
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exec_output = PredOpExecute.subst(svcIop)
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}};
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let {{
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header_output = decoder_output = exec_output = ""
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mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
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mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
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{ "code": mrsCpsrCode,
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"predicate_test": predicateTest }, [])
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header_output += MrsDeclare.subst(mrsCpsrIop)
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decoder_output += MrsConstructor.subst(mrsCpsrIop)
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exec_output += PredOpExecute.subst(mrsCpsrIop)
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mrsSpsrCode = "Dest = Spsr"
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mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
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{ "code": mrsSpsrCode,
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"predicate_test": predicateTest }, [])
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header_output += MrsDeclare.subst(mrsSpsrIop)
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decoder_output += MrsConstructor.subst(mrsSpsrIop)
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exec_output += PredOpExecute.subst(mrsSpsrIop)
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msrCpsrRegCode = '''
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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'''
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msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
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{ "code": msrCpsrRegCode,
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"predicate_test": predicateTest }, [])
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header_output += MsrRegDeclare.subst(msrCpsrRegIop)
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decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
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exec_output += PredOpExecute.subst(msrCpsrRegIop)
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msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
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msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
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{ "code": msrSpsrRegCode,
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"predicate_test": predicateTest }, [])
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header_output += MsrRegDeclare.subst(msrSpsrRegIop)
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decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
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exec_output += PredOpExecute.subst(msrSpsrRegIop)
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msrCpsrImmCode = '''
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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'''
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msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
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{ "code": msrCpsrImmCode,
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"predicate_test": predicateTest }, [])
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header_output += MsrImmDeclare.subst(msrCpsrImmIop)
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decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
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exec_output += PredOpExecute.subst(msrCpsrImmIop)
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msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
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msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
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{ "code": msrSpsrImmCode,
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"predicate_test": predicateTest }, [])
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header_output += MsrImmDeclare.subst(msrSpsrImmIop)
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decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
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exec_output += PredOpExecute.subst(msrSpsrImmIop)
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}};
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100
src/arch/arm/isa/templates/misc.isa
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100
src/arch/arm/isa/templates/misc.isa
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@ -0,0 +1,100 @@
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// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
|
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
|
||||
// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
|
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// modified or unmodified, in source code or in binary form.
|
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//
|
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// Redistribution and use in source and binary forms, with or without
|
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// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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def template MrsDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
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%(BasicExecDeclare)s
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};
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}};
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def template MrsConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
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{
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%(constructor)s;
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}
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}};
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def template MsrRegDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask);
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%(BasicExecDeclare)s
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};
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}};
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def template MsrRegConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _op1,
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uint8_t mask)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask)
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{
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%(constructor)s;
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}
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}};
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def template MsrImmDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask);
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%(BasicExecDeclare)s
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};
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}};
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def template MsrImmConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
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uint32_t imm,
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uint8_t mask)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask)
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{
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%(constructor)s;
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}
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}};
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@ -46,6 +46,9 @@
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//Templates for memory instructions
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##include "mem.isa"
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//Miscellaneous instructions that don't fit elsewhere
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##include "misc.isa"
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//Templates for microcoded memory instructions
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##include "macromem.isa"
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