ARM: Decode the load halfword, memory hints instructions for 32 bit Thumb.
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Gabe Black
parent
a483d44d9f
commit
7a9dcdf99f
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@ -140,7 +140,7 @@
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}
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0x1: decode HTOPCODE_6_5 {
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0x0: WarnUnimpl::Load_byte_memory_hints();
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0x1: WarnUnimpl::Load_halfword_memory_hints();
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0x1: LoadHalfwordMemoryHints::loadHalfwordMemoryHints();
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0x2: Thumb32LoadWord::thumb32LoadWord();
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0x3: WarnUnimpl::undefined();
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}
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@ -468,6 +468,180 @@ def format Thumb32StoreSingle() {{
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decode_block = decode % classNames
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}};
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def format LoadHalfwordMemoryHints() {{
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decode = '''
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{
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const uint32_t op1 = bits(machInst, 24, 23);
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const uint32_t op2 = bits(machInst, 11, 6);
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const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
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const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
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const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
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const uint32_t imm12 = bits(machInst, 11, 0);
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const uint32_t imm8 = bits(machInst, 7, 0);
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bool pldw = bits(machInst, 21);
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const uint32_t imm2 = bits(machInst, 5, 4);
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if (rn == 0xf) {
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if (rt == 0xf) {
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if (bits(op1, 1) == 1) {
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// Unallocated memory hint
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return new NopInst(machInst);
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} else {
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return new Unknown(machInst);
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}
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} else {
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if (bits(op1, 1) == 1) {
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if (bits(machInst, 23)) {
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return new %(ldrsh_lit_u)s(machInst, rt, INTREG_PC,
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true, imm12);
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} else {
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return new %(ldrsh_lit)s(machInst, rt, INTREG_PC,
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false, imm12);
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}
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} else {
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if (bits(machInst, 23)) {
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return new %(ldrh_lit_u)s(machInst, rt, INTREG_PC,
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true, imm12);
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} else {
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return new %(ldrh_lit)s(machInst, rt, INTREG_PC,
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false, imm12);
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}
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}
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}
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} else if (rt == 0xf) {
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switch (op1) {
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case 0x0:
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if (op2 == 0x0) {
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if (pldw) {
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return new %(pldw_radd)s(machInst, INTREG_ZERO,
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rn, true, imm2, LSL, rm);
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} else {
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return new %(pld_radd)s(machInst, INTREG_ZERO,
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rn, true, imm2, LSL, rm);
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}
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} else if (bits(op2, 5, 2) == 0xc) {
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if (pldw) {
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return new %(pldw_isub)s(machInst, INTREG_ZERO,
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rn, false, imm8);
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} else {
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return new %(pld_isub)s(machInst, INTREG_ZERO,
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rn, false, imm8);
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}
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}
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break;
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case 0x1:
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if (pldw) {
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return new %(pldw_iadd)s(machInst, INTREG_ZERO,
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rn, true, imm12);
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} else {
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return new %(pld_iadd)s(machInst, INTREG_ZERO,
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rn, true, imm12);
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}
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case 0x2:
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if (op2 == 0x0 || bits(op2, 5, 2) == 0xc) {
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// Unallocated memory hint
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return new NopInst(machInst);
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}
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break;
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case 0x3:
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return new NopInst(machInst);
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}
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return new Unknown(machInst);
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} else {
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switch (op1) {
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case 0x0:
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if (op2 == 0) {
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return new %(ldrh_radd)s(machInst, rt, rn, true,
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imm2, LSL, rm);
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} else if (bits(op2, 5, 2) == 0xe) {
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return new %(ldrht)s(machInst, rt, rn, true, imm8);
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} else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
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const uint32_t puw = bits(machInst, 10, 8);
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switch (puw) {
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case 0x1:
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return new %(ldrh_iw)s(machInst, rt,
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rn, false, imm8);
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case 0x3:
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return new %(ldrh_iuw)s(machInst, rt,
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rn, true, imm8);
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case 0x4:
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return new %(ldrh_ip)s(machInst, rt,
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rn, false, imm8);
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case 0x5:
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return new %(ldrh_ipw)s(machInst, rt,
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rn, false, imm8);
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case 0x7:
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return new %(ldrh_ipuw)s(machInst, rt,
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rn, true, imm8);
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}
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}
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break;
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case 0x1:
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return new %(ldrh_iadd)s(machInst, rt, rn, true, imm12);
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case 0x2:
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if (op2 == 0) {
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return new %(ldrsh_radd)s(machInst, rt, rn, true,
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imm2, LSL, rm);
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} else if (bits(op2, 5, 2) == 0xe) {
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return new %(ldrsht)s(machInst, rt, rn, true, imm8);
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} else if ((op2 & 0x24) == 0x24 || bits(op2, 5, 2) == 0xc) {
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const uint32_t puw = bits(machInst, 10, 8);
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switch (puw) {
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case 0x1:
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return new %(ldrsh_iw)s(machInst, rt,
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rn, false, imm8);
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case 0x3:
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return new %(ldrsh_iuw)s(machInst, rt,
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rn, true, imm8);
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case 0x4:
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return new %(ldrsh_ip)s(machInst, rt,
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rn, false, imm8);
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case 0x5:
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return new %(ldrsh_ipw)s(machInst, rt,
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rn, false, imm8);
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case 0x7:
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return new %(ldrsh_ipuw)s(machInst, rt,
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rn, true, imm8);
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}
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}
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break;
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case 0x3:
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return new %(ldrsh_iadd)s(machInst, rt, rn, true, imm12);
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}
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return new Unknown(machInst);
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}
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}
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'''
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substDict = {
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"ldrsh_lit_u" : loadImmClassName(False, True, False, 2, True),
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"ldrsh_lit" : loadImmClassName(False, False, False, 2, True),
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"ldrh_lit_u" : loadImmClassName(False, True, False, 2),
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"ldrh_lit" : loadImmClassName(False, False, False, 2),
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"ldrsh_radd" : loadRegClassName(False, True, False, 2, True),
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"ldrh_radd" : loadRegClassName(False, True, False, 2),
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"ldrsh_iw" : loadImmClassName(True, False, True, 2, True),
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"ldrsh_iuw" : loadImmClassName(True, True, True, 2, True),
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"ldrsh_ip" : loadImmClassName(False, False, False, 2, True),
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"ldrsh_ipw" : loadImmClassName(False, False, True, 2, True),
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"ldrsh_ipuw" : loadImmClassName(False, True, True, 2, True),
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"ldrsh_iadd" : loadImmClassName(False, True, False, 2, True),
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"ldrh_iw" : loadImmClassName(True, False, True, 2),
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"ldrh_iuw" : loadImmClassName(True, True, True, 2),
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"ldrh_ip" : loadImmClassName(False, False, False, 2),
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"ldrh_ipw" : loadImmClassName(False, False, True, 2),
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"ldrh_ipuw" : loadImmClassName(False, True, True, 2),
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"ldrh_iadd" : loadImmClassName(False, True, False, 2),
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"ldrht" : loadImmClassName(False, True, False, 2, user=True),
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"ldrsht" : loadImmClassName(False, True, False, 2, True, user=True),
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"pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
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"pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
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"pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
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"pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
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"pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
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"pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1)
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}
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decode_block = decode % substDict
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}};
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def format Thumb16MemReg() {{
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decode = '''
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{
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