ARM: When an instruction is intentionally undefined, fault on it.
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61a5e71be7
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bb0d390105
2 changed files with 8 additions and 8 deletions
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@ -102,7 +102,7 @@
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0x3: WarnUnimpl::Advanced_SIMD();
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default: decode LTCOPROC {
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0xa, 0xb: decode HTOPCODE_9_4 {
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0x00: WarnUnimpl::undefined();
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0x00: Unknown::undefined();
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0x04: WarnUnimpl::mcrr(); // mcrr2
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0x05: WarnUnimpl::mrrc(); // mrrc2
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0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10,
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@ -116,7 +116,7 @@
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}
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}
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default: decode HTOPCODE_9_5 {
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0x00: WarnUnimpl::undefined();
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0x00: Unknown::undefined();
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0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer();
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0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
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0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f:
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@ -142,7 +142,7 @@
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0x0: LoadByteMemoryHints::loadByteMemoryHints();
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0x1: LoadHalfwordMemoryHints::loadHalfwordMemoryHints();
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0x2: Thumb32LoadWord::thumb32LoadWord();
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0x3: WarnUnimpl::undefined();
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0x3: Unknown::undefined();
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}
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}
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0x1: decode HTOPCODE_8_7 {
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@ -170,7 +170,7 @@
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0x3: WarnUnimpl::Advanced_SIMD();
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default: decode LTCOPROC {
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0xa, 0xb: decode HTOPCODE_9_4 {
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0x00: WarnUnimpl::undefined();
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0x00: Unknown::undefined();
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0x04: WarnUnimpl::mcrr(); // mcrr2
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0x05: WarnUnimpl::mrrc(); // mrrc2
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0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10,
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@ -184,7 +184,7 @@
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}
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}
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default: decode HTOPCODE_9_5 {
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0x00: WarnUnimpl::undefined();
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0x00: Unknown::undefined();
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0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer();
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0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
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0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f:
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@ -104,7 +104,7 @@ def format Thumb16CondBranchAndSvc() {{
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return new Svc(machInst);
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} else {
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// This space will not be allocated in the future.
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return new WarnUnimplemented("unimplemented", machInst);
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return new Unknown(machInst);
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}
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'''
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}};
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@ -124,8 +124,8 @@ def format Thumb32BranchesAndMiscCtrl() {{
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case 0x0:
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if (op == 127) {
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if (op1 & 0x2) {
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// Permanentl undefined.
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return new WarnUnimplemented("undefined", machInst);
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// Permanently undefined.
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return new Unknown(machInst);
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} else {
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return new WarnUnimplemented("smc", machInst);
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}
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