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ARM: Handle accesses to TTBR0 and TTBR1.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:13 -05:00
parent b5cfa9361b
commit 951b7edaba
1 changed files with 4 additions and 4 deletions
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8
src/arch/arm/miscregs.hh
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@ -106,6 +106,8 @@ namespace ArmISA
MISCREG_BPIALLIS,
MISCREG_BPIALL,
MISCREG_MIDR,
MISCREG_TTBR0,
MISCREG_TTBR1,
MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START,
MISCREG_TLBTR,
@ -142,8 +144,6 @@ namespace ArmISA
MISCREG_SCR,
MISCREG_SDER,
MISCREG_NSACR,
MISCREG_TTBR0,
MISCREG_TTBR1,
MISCREG_TTBCR,
MISCREG_V2PCWPR,
MISCREG_V2PCWPW,
@ -198,7 +198,7 @@ namespace ArmISA
"clidr", "ccsidr", "csselr",
"icialluis", "iciallu", "icimvau",
"bpimva", "bpiallis", "bpiall",
"midr", "ctr", "tlbtr", "tcmtr", "mpidr",
"midr", "ttbr0", "ttbr1", "ctr", "tlbtr", "tcmtr", "mpidr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
@ -206,7 +206,7 @@ namespace ArmISA
"dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
"dcimvac", "dcisw", "mccsw",
"dccmvau",
"scr", "sder", "nsacr", "ttbr0", "ttbr1", "ttbcr",
"scr", "sder", "nsacr", "ttbcr",
"v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
"v2powpr", "v2powpw", "v2powur", "v2powuw",
"tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",