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ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:05 -05:00
parent f0811eb208
commit ff3b21bc2b
2 changed files with 38 additions and 33 deletions
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34
src/arch/arm/isa/decoder/arm.isa
View file

@ -71,39 +71,7 @@ format DataOp {
0: ArmDataProcReg::armDataProcReg();
1: decode OPCODE_7 {
0x0: decode MISC_OPCODE {
0x0: decode OPCODE {
0x8: PredOp::mrs_cpsr({{
Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
}});
0x9: decode USEIMM {
// The mask field is the same as the RN index.
0: PredOp::msr_cpsr_reg({{
uint32_t newCpsr =
cpsrWriteByInstr(Cpsr | CondCodes,
Rm, RN, false);
Cpsr = ~CondCodesMask & newCpsr;
CondCodes = CondCodesMask & newCpsr;
}});
1: PredImmOp::msr_cpsr_imm({{
uint32_t newCpsr =
cpsrWriteByInstr(Cpsr | CondCodes,
rotated_imm, RN, false);
Cpsr = ~CondCodesMask & newCpsr;
CondCodes = CondCodesMask & newCpsr;
}});
}
0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
0xb: decode USEIMM {
// The mask field is the same as the RN index.
0: PredOp::msr_spsr_reg({{
Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
}});
1: PredImmOp::msr_spsr_imm({{
Spsr = spsrWriteByInstr(Spsr, rotated_imm,
RN, false);
}});
}
}
0x0: ArmMsrMrs::armMsrMrs();
0x1: decode OPCODE {
0x9: ArmBx::armBx();
0xb: PredOp::clz({{

37
src/arch/arm/isa/formats/misc.isa
View file

@ -40,3 +40,40 @@
def format Svc() {{
decode_block = "return new Svc(machInst);"
}};
def format ArmMsrMrs() {{
decode_block = '''
{
const uint8_t byteMask = bits(machInst, 19, 16);
const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
const uint32_t opcode = bits(machInst, 24, 21);
const bool useImm = bits(machInst, 25);
const uint32_t unrotated = bits(machInst, 7, 0);
const uint32_t rotation = (bits(machInst, 11, 8) << 1);
const uint32_t imm = rotate_imm(unrotated, rotation);
switch (opcode) {
case 0x8:
return new MrsCpsr(machInst, rd);
case 0x9:
if (useImm) {
return new MsrCpsrImm(machInst, imm, byteMask);
} else {
return new MsrCpsrReg(machInst, rn, byteMask);
}
case 0xa:
return new MrsSpsr(machInst, rd);
case 0xb:
if (useImm) {
return new MsrSpsrImm(machInst, imm, byteMask);
} else {
return new MsrSpsrReg(machInst, rn, byteMask);
}
default:
return new Unknown(machInst);
}
}
'''
}};