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ARM: Move the longer MemoryReg::printoffset function in mem.hh into the cc file.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:18 -05:00
parent 9223725973
commit 0abec53564
2 changed files with 37 additions and 35 deletions
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36
src/arch/arm/insts/mem.cc
View file

@ -48,6 +48,42 @@ using namespace std;
namespace ArmISA
{
void
MemoryReg::printOffset(std::ostream &os) const
{
if (!add)
os << "-";
printReg(os, index);
if (shiftType != LSL || shiftAmt != 0) {
switch (shiftType) {
case LSL:
ccprintf(os, " LSL #%d", shiftAmt);
break;
case LSR:
if (shiftAmt == 0) {
ccprintf(os, " LSR #%d", 32);
} else {
ccprintf(os, " LSR #%d", shiftAmt);
}
break;
case ASR:
if (shiftAmt == 0) {
ccprintf(os, " ASR #%d", 32);
} else {
ccprintf(os, " ASR #%d", shiftAmt);
}
break;
case ROR:
if (shiftAmt == 0) {
ccprintf(os, " RRX");
} else {
ccprintf(os, " ROR #%d", shiftAmt);
}
break;
}
}
}
string
Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{

36
src/arch/arm/insts/mem.hh
View file

@ -246,41 +246,7 @@ class MemoryReg : public Memory
shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index)
{}
void
printOffset(std::ostream &os) const
{
if (!add)
os << "-";
printReg(os, index);
if (shiftType != LSL || shiftAmt != 0) {
switch (shiftType) {
case LSL:
ccprintf(os, " LSL #%d", shiftAmt);
break;
case LSR:
if (shiftAmt == 0) {
ccprintf(os, " LSR #%d", 32);
} else {
ccprintf(os, " LSR #%d", shiftAmt);
}
break;
case ASR:
if (shiftAmt == 0) {
ccprintf(os, " ASR #%d", 32);
} else {
ccprintf(os, " ASR #%d", shiftAmt);
}
break;
case ROR:
if (shiftAmt == 0) {
ccprintf(os, " RRX");
} else {
ccprintf(os, " ROR #%d", shiftAmt);
}
break;
}
}
}
void printOffset(std::ostream &os) const;
};
class MemoryDReg : public MemoryReg