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ARM: Implement a version of mcr and mrc that works in user mode.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:17 -05:00
parent e91e6ff9a4
commit 6101e1b062
2 changed files with 33 additions and 0 deletions
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19
src/arch/arm/isa/formats/misc.isa
View file

@ -137,6 +137,8 @@ let {{
case MISCREG_BPIALL:
return new WarnUnimplemented(
isRead ? "mrc bpiall" : "mcr bpiall", machInst);
// Write only.
case MISCREG_TLBIALLIS:
case MISCREG_TLBIMVAIS:
case MISCREG_TLBIASIDIS:
@ -157,6 +159,23 @@ let {{
return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
}
// Read only in user mode.
case MISCREG_TPIDRURO:
if (isRead) {
return new Mrc15User(machInst, rt, (IntRegIndex)miscReg);
} else {
return new Mcr15(machInst, (IntRegIndex)miscReg, rt);
}
// Read/write in user mode.
case MISCREG_TPIDRURW:
if (isRead) {
return new Mrc15User(machInst, rt, (IntRegIndex)miscReg);
} else {
return new Mcr15User(machInst, (IntRegIndex)miscReg, rt);
}
// Read/write, priveleged only.
default:
if (isRead) {
return new Mrc15(machInst, rt, (IntRegIndex)miscReg);

14
src/arch/arm/isa/insts/misc.isa
View file

@ -614,6 +614,20 @@ let {{
decoder_output += RegRegOpConstructor.subst(mcr15Iop)
exec_output += PredOpExecute.subst(mcr15Iop)
mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
{ "code": "Dest = MiscOp1;",
"predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(mrc15UserIop)
decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
exec_output += PredOpExecute.subst(mrc15UserIop)
mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
{ "code": "MiscDest = Op1",
"predicate_test": predicateTest }, [])
header_output += RegRegOpDeclare.subst(mcr15UserIop)
decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
exec_output += PredOpExecute.subst(mcr15UserIop)
enterxCode = '''
FNPC = NPC | (1ULL << PcJBitShift) | (1ULL << PcTBitShift);
'''