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ARM: Add a base class for the sel instruction.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:07 -05:00
parent f581fd3f89
commit 498f9d925e
3 changed files with 53 additions and 0 deletions
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13
src/arch/arm/insts/misc.cc
View file

@ -168,6 +168,19 @@ RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
return ss.str();
}
std::string
RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
ss << ", ";
printReg(ss, op1);
ss << ", ";
printReg(ss, op2);
return ss.str();
}
std::string
RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{

16
src/arch/arm/insts/misc.hh
View file

@ -142,6 +142,22 @@ class RegRegRegImmOp : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class RegRegRegOp : public PredOp
{
protected:
IntRegIndex dest;
IntRegIndex op1;
IntRegIndex op2;
RegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2)
{}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class RegImmRegShiftOp : public PredOp
{
protected:

24
src/arch/arm/isa/templates/misc.isa
View file

@ -146,6 +146,30 @@ def template RegRegRegImmOpConstructor {{
}
}};
def template RegRegRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
protected:
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2);
%(BasicExecDeclare)s
};
}};
def template RegRegRegOpConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2)
{
%(constructor)s;
}
}};
def template RegImmRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{