ARM: Implement the floating/fixed point VCVT instructions.
This commit is contained in:
Gabe Black
parent
86a1093992
commit
aa05e5401c
3 changed files with 463 additions and 4 deletions
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@ -101,6 +101,150 @@ enum VfpRoundingMode
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VfpRoundZero = 3
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};
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static inline uint64_t
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vfpFpSToFixed(float val, bool isSigned, bool half, uint8_t imm)
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{
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fesetround(FeRoundZero);
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val = val * powf(2.0, imm);
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__asm__ __volatile__("" : "=m" (val) : "m" (val));
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feclearexcept(FeAllExceptions);
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if (isSigned) {
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if (half) {
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if (val < (int16_t)(1 << 15)) {
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feraiseexcept(FeInvalid);
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return (int16_t)(1 << 15);
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}
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if (val > (int16_t)mask(15)) {
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feraiseexcept(FeInvalid);
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return (int16_t)mask(15);
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}
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return (int16_t)val;
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} else {
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if (val < (int32_t)(1 << 31)) {
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feraiseexcept(FeInvalid);
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return (int32_t)(1 << 31);
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}
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if (val > (int32_t)mask(31)) {
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feraiseexcept(FeInvalid);
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return (int32_t)mask(31);
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}
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return (int32_t)val;
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}
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} else {
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if (half) {
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if (val < 0) {
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feraiseexcept(FeInvalid);
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return 0;
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}
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if (val > (mask(16))) {
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feraiseexcept(FeInvalid);
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return mask(16);
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}
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return (uint16_t)val;
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} else {
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if (val < 0) {
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feraiseexcept(FeInvalid);
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return 0;
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}
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if (val > (mask(32))) {
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feraiseexcept(FeInvalid);
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return mask(32);
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}
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return (uint32_t)val;
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}
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}
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}
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static inline float
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vfpUFixedToFpS(uint32_t val, bool half, uint8_t imm)
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{
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fesetround(FeRoundNearest);
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if (half)
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val = (uint16_t)val;
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return val / powf(2.0, imm);
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}
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static inline float
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vfpSFixedToFpS(int32_t val, bool half, uint8_t imm)
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{
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fesetround(FeRoundNearest);
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if (half)
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val = sext<16>(val & mask(16));
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return val / powf(2.0, imm);
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}
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static inline uint64_t
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vfpFpDToFixed(double val, bool isSigned, bool half, uint8_t imm)
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{
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fesetround(FeRoundZero);
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val = val * pow(2.0, imm);
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__asm__ __volatile__("" : "=m" (val) : "m" (val));
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feclearexcept(FeAllExceptions);
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if (isSigned) {
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if (half) {
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if (val < (int16_t)(1 << 15)) {
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feraiseexcept(FeInvalid);
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return (int16_t)(1 << 15);
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}
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if (val > (int16_t)mask(15)) {
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feraiseexcept(FeInvalid);
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return (int16_t)mask(15);
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}
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return (int16_t)val;
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} else {
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if (val < (int32_t)(1 << 31)) {
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feraiseexcept(FeInvalid);
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return (int32_t)(1 << 31);
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}
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if (val > (int32_t)mask(31)) {
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feraiseexcept(FeInvalid);
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return (int32_t)mask(31);
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}
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return (int32_t)val;
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}
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} else {
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if (half) {
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if (val < 0) {
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feraiseexcept(FeInvalid);
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return 0;
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}
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if (val > mask(16)) {
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feraiseexcept(FeInvalid);
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return mask(16);
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}
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return (uint16_t)val;
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} else {
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if (val < 0) {
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feraiseexcept(FeInvalid);
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return 0;
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}
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if (val > mask(32)) {
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feraiseexcept(FeInvalid);
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return mask(32);
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}
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return (uint32_t)val;
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}
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}
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}
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static inline double
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vfpUFixedToFpD(uint32_t val, bool half, uint8_t imm)
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{
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fesetround(FeRoundNearest);
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if (half)
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val = (uint16_t)val;
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return val / pow(2.0, imm);
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}
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static inline double
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vfpSFixedToFpD(int32_t val, bool half, uint8_t imm)
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{
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fesetround(FeRoundNearest);
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if (half)
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val = sext<16>(val & mask(16));
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return val / pow(2.0, imm);
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}
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typedef int VfpSavedState;
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static inline VfpSavedState
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@ -683,9 +683,47 @@ let {{
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}
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}
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case 0xa:
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{
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const bool half = (bits(machInst, 7) == 0);
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const uint32_t imm = bits(machInst, 5) |
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(bits(machInst, 3, 0) << 1);
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const uint32_t size =
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(bits(machInst, 7) == 0 ? 16 : 32) - imm;
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if (single) {
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if (half) {
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return new VcvtSHFixedFpS(machInst, vd, vd, size);
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} else {
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return new VcvtSFixedFpS(machInst, vd, vd, size);
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}
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} else {
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if (half) {
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return new VcvtSHFixedFpD(machInst, vd, vd, size);
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} else {
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return new VcvtSFixedFpD(machInst, vd, vd, size);
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}
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}
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}
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case 0xb:
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// Between FP and fixed point.
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return new WarnUnimplemented("vcvt", machInst);
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{
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const bool half = (bits(machInst, 7) == 0);
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const uint32_t imm = bits(machInst, 5) |
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(bits(machInst, 3, 0) << 1);
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const uint32_t size =
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(bits(machInst, 7) == 0 ? 16 : 32) - imm;
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if (single) {
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if (half) {
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return new VcvtUHFixedFpS(machInst, vd, vd, size);
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} else {
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return new VcvtUFixedFpS(machInst, vd, vd, size);
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}
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} else {
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if (half) {
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return new VcvtUHFixedFpD(machInst, vd, vd, size);
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} else {
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return new VcvtUFixedFpD(machInst, vd, vd, size);
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}
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}
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}
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case 0xc:
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if (single) {
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return new VcvtFpUIntS(machInst, vd, vm);
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@ -703,9 +741,47 @@ let {{
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return new VcvtFpSIntD(machInst, vd, vm);
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}
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case 0xe:
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{
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const bool half = (bits(machInst, 7) == 0);
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const uint32_t imm = bits(machInst, 5) |
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(bits(machInst, 3, 0) << 1);
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const uint32_t size =
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(bits(machInst, 7) == 0 ? 16 : 32) - imm;
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if (single) {
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if (half) {
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return new VcvtFpSHFixedS(machInst, vd, vd, size);
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} else {
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return new VcvtFpSFixedS(machInst, vd, vd, size);
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}
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} else {
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if (half) {
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return new VcvtFpSHFixedD(machInst, vd, vd, size);
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} else {
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return new VcvtFpSFixedD(machInst, vd, vd, size);
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}
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}
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}
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case 0xf:
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// Between FP and fixed point.
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return new WarnUnimplemented("vcvt", machInst);
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{
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const bool half = (bits(machInst, 7) == 0);
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const uint32_t imm = bits(machInst, 5) |
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(bits(machInst, 3, 0) << 1);
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const uint32_t size =
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(bits(machInst, 7) == 0 ? 16 : 32) - imm;
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if (single) {
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if (half) {
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return new VcvtFpUHFixedS(machInst, vd, vd, size);
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} else {
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return new VcvtFpUFixedS(machInst, vd, vd, size);
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}
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} else {
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if (half) {
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return new VcvtFpUHFixedD(machInst, vd, vd, size);
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} else {
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return new VcvtFpUFixedD(machInst, vd, vd, size);
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}
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}
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}
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}
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break;
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}
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@ -997,3 +997,242 @@ let {{
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decoder_output += VfpRegImmOpConstructor.subst(vcmpZeroDIop);
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exec_output += PredOpExecute.subst(vcmpZeroDIop);
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}};
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let {{
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header_output = ""
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decoder_output = ""
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exec_output = ""
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vcvtFpSFixedSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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FpDest.sw = vfpFpSToFixed(FpOp1, true, false, imm);
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Fpscr = setVfpFpscr(Fpscr, state);
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'''
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vcvtFpSFixedSIop = InstObjParams("vcvt", "VcvtFpSFixedS", "VfpRegRegImmOp",
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{ "code": vcvtFpSFixedSCode,
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"predicate_test": predicateTest }, [])
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header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedSIop);
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decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedSIop);
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exec_output += PredOpExecute.subst(vcvtFpSFixedSIop);
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vcvtFpSFixedDCode = '''
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IntDoubleUnion cOp1;
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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VfpSavedState state = prepVfpFpscr(Fpscr);
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uint64_t mid = vfpFpDToFixed(cOp1.fp, true, false, imm);
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Fpscr = setVfpFpscr(Fpscr, state);
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FpDestP0.uw = mid;
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FpDestP1.uw = mid >> 32;
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'''
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vcvtFpSFixedDIop = InstObjParams("vcvt", "VcvtFpSFixedD", "VfpRegRegImmOp",
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{ "code": vcvtFpSFixedDCode,
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"predicate_test": predicateTest }, [])
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header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSFixedDIop);
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decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSFixedDIop);
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exec_output += PredOpExecute.subst(vcvtFpSFixedDIop);
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vcvtFpUFixedSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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FpDest.uw = vfpFpSToFixed(FpOp1, false, false, imm);
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Fpscr = setVfpFpscr(Fpscr, state);
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'''
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vcvtFpUFixedSIop = InstObjParams("vcvt", "VcvtFpUFixedS", "VfpRegRegImmOp",
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{ "code": vcvtFpUFixedSCode,
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"predicate_test": predicateTest }, [])
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header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedSIop);
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decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedSIop);
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exec_output += PredOpExecute.subst(vcvtFpUFixedSIop);
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vcvtFpUFixedDCode = '''
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IntDoubleUnion cOp1;
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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VfpSavedState state = prepVfpFpscr(Fpscr);
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uint64_t mid = vfpFpDToFixed(cOp1.fp, false, false, imm);
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Fpscr = setVfpFpscr(Fpscr, state);
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FpDestP0.uw = mid;
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FpDestP1.uw = mid >> 32;
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'''
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vcvtFpUFixedDIop = InstObjParams("vcvt", "VcvtFpUFixedD", "VfpRegRegImmOp",
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{ "code": vcvtFpUFixedDCode,
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"predicate_test": predicateTest }, [])
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header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUFixedDIop);
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decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUFixedDIop);
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exec_output += PredOpExecute.subst(vcvtFpUFixedDIop);
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vcvtSFixedFpSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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FpDest = vfpSFixedToFpS(FpOp1.sw, true, imm);
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Fpscr = setVfpFpscr(Fpscr, state);
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'''
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vcvtSFixedFpSIop = InstObjParams("vcvt", "VcvtSFixedFpS", "VfpRegRegImmOp",
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{ "code": vcvtSFixedFpSCode,
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"predicate_test": predicateTest }, [])
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header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpSIop);
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decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpSIop);
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exec_output += PredOpExecute.subst(vcvtSFixedFpSIop);
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vcvtSFixedFpDCode = '''
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IntDoubleUnion cDest;
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uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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VfpSavedState state = prepVfpFpscr(Fpscr);
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cDest.fp = vfpSFixedToFpD(mid, true, imm);
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Fpscr = setVfpFpscr(Fpscr, state);
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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vcvtSFixedFpDIop = InstObjParams("vcvt", "VcvtSFixedFpD", "VfpRegRegImmOp",
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{ "code": vcvtSFixedFpDCode,
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"predicate_test": predicateTest }, [])
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header_output += VfpRegRegImmOpDeclare.subst(vcvtSFixedFpDIop);
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decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSFixedFpDIop);
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exec_output += PredOpExecute.subst(vcvtSFixedFpDIop);
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vcvtUFixedFpSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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FpDest = vfpUFixedToFpS(FpOp1.uw, false, imm);
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Fpscr = setVfpFpscr(Fpscr, state);
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'''
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vcvtUFixedFpSIop = InstObjParams("vcvt", "VcvtUFixedFpS", "VfpRegRegImmOp",
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{ "code": vcvtUFixedFpSCode,
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"predicate_test": predicateTest }, [])
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header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpSIop);
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decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpSIop);
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exec_output += PredOpExecute.subst(vcvtUFixedFpSIop);
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vcvtUFixedFpDCode = '''
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IntDoubleUnion cDest;
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uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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VfpSavedState state = prepVfpFpscr(Fpscr);
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cDest.fp = vfpUFixedToFpD(mid, false, imm);
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Fpscr = setVfpFpscr(Fpscr, state);
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FpDestP0.uw = cDest.bits;
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FpDestP1.uw = cDest.bits >> 32;
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'''
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vcvtUFixedFpDIop = InstObjParams("vcvt", "VcvtUFixedFpD", "VfpRegRegImmOp",
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{ "code": vcvtUFixedFpDCode,
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"predicate_test": predicateTest }, [])
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header_output += VfpRegRegImmOpDeclare.subst(vcvtUFixedFpDIop);
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decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUFixedFpDIop);
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exec_output += PredOpExecute.subst(vcvtUFixedFpDIop);
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vcvtFpSHFixedSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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FpDest.sh = vfpFpSToFixed(FpOp1, true, true, imm);
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Fpscr = setVfpFpscr(Fpscr, state);
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'''
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vcvtFpSHFixedSIop = InstObjParams("vcvt", "VcvtFpSHFixedS",
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"VfpRegRegImmOp",
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{ "code": vcvtFpSHFixedSCode,
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"predicate_test": predicateTest }, [])
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header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedSIop);
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decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedSIop);
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exec_output += PredOpExecute.subst(vcvtFpSHFixedSIop);
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vcvtFpSHFixedDCode = '''
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IntDoubleUnion cOp1;
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cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
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VfpSavedState state = prepVfpFpscr(Fpscr);
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uint64_t result = vfpFpDToFixed(cOp1.fp, true, true, imm);
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Fpscr = setVfpFpscr(Fpscr, state);
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FpDestP0.uw = result;
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FpDestP1.uw = result >> 32;
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'''
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vcvtFpSHFixedDIop = InstObjParams("vcvt", "VcvtFpSHFixedD",
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"VfpRegRegImmOp",
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{ "code": vcvtFpSHFixedDCode,
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"predicate_test": predicateTest }, [])
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header_output += VfpRegRegImmOpDeclare.subst(vcvtFpSHFixedDIop);
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decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpSHFixedDIop);
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exec_output += PredOpExecute.subst(vcvtFpSHFixedDIop);
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vcvtFpUHFixedSCode = '''
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VfpSavedState state = prepVfpFpscr(Fpscr);
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FpDest.uh = vfpFpSToFixed(FpOp1, false, true, imm);
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Fpscr = setVfpFpscr(Fpscr, state);
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'''
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vcvtFpUHFixedSIop = InstObjParams("vcvt", "VcvtFpUHFixedS",
|
||||
"VfpRegRegImmOp",
|
||||
{ "code": vcvtFpUHFixedSCode,
|
||||
"predicate_test": predicateTest }, [])
|
||||
header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedSIop);
|
||||
decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedSIop);
|
||||
exec_output += PredOpExecute.subst(vcvtFpUHFixedSIop);
|
||||
|
||||
vcvtFpUHFixedDCode = '''
|
||||
IntDoubleUnion cOp1;
|
||||
cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
|
||||
VfpSavedState state = prepVfpFpscr(Fpscr);
|
||||
uint64_t mid = vfpFpDToFixed(cOp1.fp, false, true, imm);
|
||||
Fpscr = setVfpFpscr(Fpscr, state);
|
||||
FpDestP0.uw = mid;
|
||||
FpDestP1.uw = mid >> 32;
|
||||
'''
|
||||
vcvtFpUHFixedDIop = InstObjParams("vcvt", "VcvtFpUHFixedD",
|
||||
"VfpRegRegImmOp",
|
||||
{ "code": vcvtFpUHFixedDCode,
|
||||
"predicate_test": predicateTest }, [])
|
||||
header_output += VfpRegRegImmOpDeclare.subst(vcvtFpUHFixedDIop);
|
||||
decoder_output += VfpRegRegImmOpConstructor.subst(vcvtFpUHFixedDIop);
|
||||
exec_output += PredOpExecute.subst(vcvtFpUHFixedDIop);
|
||||
|
||||
vcvtSHFixedFpSCode = '''
|
||||
VfpSavedState state = prepVfpFpscr(Fpscr);
|
||||
FpDest = vfpSFixedToFpS(FpOp1.sh, true, imm);
|
||||
Fpscr = setVfpFpscr(Fpscr, state);
|
||||
'''
|
||||
vcvtSHFixedFpSIop = InstObjParams("vcvt", "VcvtSHFixedFpS",
|
||||
"VfpRegRegImmOp",
|
||||
{ "code": vcvtSHFixedFpSCode,
|
||||
"predicate_test": predicateTest }, [])
|
||||
header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpSIop);
|
||||
decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpSIop);
|
||||
exec_output += PredOpExecute.subst(vcvtSHFixedFpSIop);
|
||||
|
||||
vcvtSHFixedFpDCode = '''
|
||||
IntDoubleUnion cDest;
|
||||
uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
|
||||
VfpSavedState state = prepVfpFpscr(Fpscr);
|
||||
cDest.fp = vfpSFixedToFpD(mid, true, imm);
|
||||
Fpscr = setVfpFpscr(Fpscr, state);
|
||||
FpDestP0.uw = cDest.bits;
|
||||
FpDestP1.uw = cDest.bits >> 32;
|
||||
'''
|
||||
vcvtSHFixedFpDIop = InstObjParams("vcvt", "VcvtSHFixedFpD",
|
||||
"VfpRegRegImmOp",
|
||||
{ "code": vcvtSHFixedFpDCode,
|
||||
"predicate_test": predicateTest }, [])
|
||||
header_output += VfpRegRegImmOpDeclare.subst(vcvtSHFixedFpDIop);
|
||||
decoder_output += VfpRegRegImmOpConstructor.subst(vcvtSHFixedFpDIop);
|
||||
exec_output += PredOpExecute.subst(vcvtSHFixedFpDIop);
|
||||
|
||||
vcvtUHFixedFpSCode = '''
|
||||
VfpSavedState state = prepVfpFpscr(Fpscr);
|
||||
FpDest = vfpUFixedToFpS(FpOp1.uh, true, imm);
|
||||
Fpscr = setVfpFpscr(Fpscr, state);
|
||||
'''
|
||||
vcvtUHFixedFpSIop = InstObjParams("vcvt", "VcvtUHFixedFpS",
|
||||
"VfpRegRegImmOp",
|
||||
{ "code": vcvtUHFixedFpSCode,
|
||||
"predicate_test": predicateTest }, [])
|
||||
header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpSIop);
|
||||
decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpSIop);
|
||||
exec_output += PredOpExecute.subst(vcvtUHFixedFpSIop);
|
||||
|
||||
vcvtUHFixedFpDCode = '''
|
||||
IntDoubleUnion cDest;
|
||||
uint64_t mid = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
|
||||
VfpSavedState state = prepVfpFpscr(Fpscr);
|
||||
cDest.fp = vfpUFixedToFpD(mid, true, imm);
|
||||
Fpscr = setVfpFpscr(Fpscr, state);
|
||||
FpDestP0.uw = cDest.bits;
|
||||
FpDestP1.uw = cDest.bits >> 32;
|
||||
'''
|
||||
vcvtUHFixedFpDIop = InstObjParams("vcvt", "VcvtUHFixedFpD",
|
||||
"VfpRegRegImmOp",
|
||||
{ "code": vcvtUHFixedFpDCode,
|
||||
"predicate_test": predicateTest }, [])
|
||||
header_output += VfpRegRegImmOpDeclare.subst(vcvtUHFixedFpDIop);
|
||||
decoder_output += VfpRegRegImmOpConstructor.subst(vcvtUHFixedFpDIop);
|
||||
exec_output += PredOpExecute.subst(vcvtUHFixedFpDIop);
|
||||
}};
|
||||
|
|
|
|||
Loading…
Reference in a new issue