ARM: Make sure macroops aren't interrupted midinstruction.
Do this by setting the delayed commit flag for all but the last microop.
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parent
67766cbf17
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1fcd389fa3
2 changed files with 32 additions and 2 deletions
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@ -128,6 +128,13 @@ MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
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}
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(*uop)->setLastMicroop();
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for (StaticInstPtr *curUop = microOps;
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!(*curUop)->isLastMicroop(); curUop++) {
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MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get());
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assert(uopPtr);
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uopPtr->setDelayedCommit();
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}
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}
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MacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst,
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@ -198,6 +205,13 @@ MacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst,
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assert(numMicroops == i);
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microOps[numMicroops - 1]->setLastMicroop();
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for (StaticInstPtr *curUop = microOps;
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!(*curUop)->isLastMicroop(); curUop++) {
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MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get());
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assert(uopPtr);
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uopPtr->setDelayedCommit();
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}
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}
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}
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@ -60,10 +60,26 @@ number_of_ones(int32_t val)
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return ones;
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}
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class MicroOp : public PredOp
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{
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protected:
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MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass)
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: PredOp(mnem, machInst, __opClass)
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{
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}
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public:
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void
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setDelayedCommit()
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{
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flags[IsDelayedCommit] = true;
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}
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};
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/**
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* Microops of the form IntRegA = IntRegB op Imm
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*/
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class MicroIntOp : public PredOp
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class MicroIntOp : public MicroOp
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{
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protected:
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RegIndex ura, urb;
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@ -71,7 +87,7 @@ class MicroIntOp : public PredOp
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MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
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RegIndex _ura, RegIndex _urb, uint8_t _imm)
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: PredOp(mnem, machInst, __opClass),
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: MicroOp(mnem, machInst, __opClass),
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ura(_ura), urb(_urb), imm(_imm)
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{
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}
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