sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

ARM: Warn/ignore when TLB maintenance operations are performed.

Browse source
This commit is contained in:
Gabe Black 2010-06-02 12:58:13 -05:00
parent eac239b4d6
commit e21f93702a
2 changed files with 62 additions and 19 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

42
src/arch/arm/isa/formats/misc.isa
View file

@ -128,6 +128,48 @@ def format McrMrc15() {{
case MISCREG_BPIALL:
return new WarnUnimplemented(
isRead ? "mrc bpiall" : "mcr bpiall", machInst);
case MISCREG_TLBIALLIS:
return new WarnUnimplemented(
isRead ? "mrc tlbiallis" : "mcr tlbiallis", machInst);
case MISCREG_TLBIMVAIS:
return new WarnUnimplemented(
isRead ? "mrc tlbimvais" : "mcr tlbimvais", machInst);
case MISCREG_TLBIASIDIS:
return new WarnUnimplemented(
isRead ? "mrc tlbiasidis" : "mcr tlbiasidis", machInst);
case MISCREG_TLBIMVAAIS:
return new WarnUnimplemented(
isRead ? "mrc tlbimvaais" : "mcr tlbimvaais", machInst);
case MISCREG_ITLBIALL:
return new WarnUnimplemented(
isRead ? "mrc itlbiall" : "mcr itlbiall", machInst);
case MISCREG_ITLBIMVA:
return new WarnUnimplemented(
isRead ? "mrc itlbimva" : "mcr itlbimva", machInst);
case MISCREG_ITLBIASID:
return new WarnUnimplemented(
isRead ? "mrc itlbiasid" : "mcr itlbiasid", machInst);
case MISCREG_DTLBIALL:
return new WarnUnimplemented(
isRead ? "mrc dtlbiall" : "mcr dtlbiall", machInst);
case MISCREG_DTLBIMVA:
return new WarnUnimplemented(
isRead ? "mrc dtlbimva" : "mcr dtlbimva", machInst);
case MISCREG_DTLBIASID:
return new WarnUnimplemented(
isRead ? "mrc dtlbiasid" : "mcr dtlbiasid", machInst);
case MISCREG_TLBIALL:
return new WarnUnimplemented(
isRead ? "mrc tlbiall" : "mcr tlbiall", machInst);
case MISCREG_TLBIMVA:
return new WarnUnimplemented(
isRead ? "mrc tlbimva" : "mcr tlbimva", machInst);
case MISCREG_TLBIASID:
return new WarnUnimplemented(
isRead ? "mrc tlbiasid" : "mcr tlbiasid", machInst);
case MISCREG_TLBIMVAA:
return new WarnUnimplemented(
isRead ? "mrc tlbimvaa" : "mcr tlbimvaa", machInst);
default:
if (isRead) {
return new Mrc15(machInst, rt, (IntRegIndex)miscReg);

39
src/arch/arm/miscregs.hh
View file

@ -110,6 +110,20 @@ namespace ArmISA
MISCREG_TTBR1,
MISCREG_TLBTR,
MISCREG_DACR,
MISCREG_TLBIALLIS,
MISCREG_TLBIMVAIS,
MISCREG_TLBIASIDIS,
MISCREG_TLBIMVAAIS,
MISCREG_ITLBIALL,
MISCREG_ITLBIMVA,
MISCREG_ITLBIASID,
MISCREG_DTLBIALL,
MISCREG_DTLBIMVA,
MISCREG_DTLBIASID,
MISCREG_TLBIALL,
MISCREG_TLBIMVA,
MISCREG_TLBIASID,
MISCREG_TLBIMVAA,
MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR,
@ -153,20 +167,6 @@ namespace ArmISA
MISCREG_V2POWPW,
MISCREG_V2POWUR,
MISCREG_V2POWUW,
MISCREG_TLBIALLIS,
MISCREG_TLBIMVAIS,
MISCREG_TLBIASIDIS,
MISCREG_TLBIMVAAIS,
MISCREG_ITLBIALL,
MISCREG_ITLBIMVA,
MISCREG_ITLBIASID,
MISCREG_DTLBIALL,
MISCREG_DTLBIMVA,
MISCREG_DTLBIASID,
MISCREG_TLBIALL,
MISCREG_TLBIMVA,
MISCREG_TLBIASID,
MISCREG_TLBIMVAA,
MISCREG_PRRR,
MISCREG_NMRR,
MISCREG_VBAR,
@ -198,7 +198,12 @@ namespace ArmISA
"clidr", "ccsidr", "csselr",
"icialluis", "iciallu", "icimvau",
"bpimva", "bpiallis", "bpiall",
"midr", "ttbr0", "ttbr1", "tlbtr", "dacr", "ctr", "tcmtr", "mpidr",
"midr", "ttbr0", "ttbr1", "tlbtr", "dacr",
"tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
"itlbiall", "itlbimva", "itlbiasid",
"dtlbiall", "dtlbimva", "dtlbiasid",
"tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
"ctr", "tcmtr", "mpidr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
@ -209,10 +214,6 @@ namespace ArmISA
"scr", "sder", "nsacr", "ttbcr",
"v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
"v2powpr", "v2powpw", "v2powur", "v2powuw",
"tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
"itlbiall", "itlbimva", "itlbiasid",
"dtlbiall", "dtlbimva", "dtlbiasid",
"tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
"prrr", "nmrr", "vbar", "mvbar", "isr", "fceidr",
"nop", "raz"
};